liteeth/mac/wishbone: Fix write_only mode on RX.
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@ -46,7 +46,7 @@ class LiteEthMACWishboneInterface(LiteXModule):
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mems = self.sram.writer.mems,
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mems = self.sram.writer.mems,
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nslots = nrxslots,
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nslots = nrxslots,
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read_only = rxslots_read_only,
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read_only = rxslots_read_only,
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write_only = True,
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write_only = False,
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)
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)
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self._expose_wishbone_sram_interfaces(
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self._expose_wishbone_sram_interfaces(
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bus = self.bus_tx,
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bus = self.bus_tx,
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