phy/efinix: Switch to new DDROutput/Input now supported in LiteX for Efinix.
This commit is contained in:
Florent Kermarrec
parent
b201aeb083
commit
8436d775f6
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@ -12,6 +12,7 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.gen import *
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from litex.gen import *
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from litex.build.io import DDROutput, DDRInput
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from litex.build.generic_platform import *
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from litex.build.generic_platform import *
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from litex.soc.cores.clock import *
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from litex.soc.cores.clock import *
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@ -21,71 +22,49 @@ from liteeth.phy.common import *
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# LiteEth PHY RGMII TX -----------------------------------------------------------------------------
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# LiteEth PHY RGMII TX -----------------------------------------------------------------------------
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class LiteEthPHYRGMIITX(LiteXModule):
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class LiteEthPHYRGMIITX(LiteXModule):
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def __init__(self, platform, pads):
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def __init__(self, platform, pads, ddr_tx_ctl=True):
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self.sink = sink = stream.Endpoint(eth_phy_description(8))
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self.sink = sink = stream.Endpoint(eth_phy_description(8))
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# # #
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# # #
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# TX Data IOs.
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# TX Data IOs.
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# ------------
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# ------------
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tx_data_h = []
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tx_data_h = Signal(4)
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tx_data_l = []
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tx_data_l = Signal(4)
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for n in range(4):
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for n in range(4):
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name = platform.get_pin_name(pads.tx_data[n])
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self.specials += DDROutput(
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pad = platform.get_pin_location(pads.tx_data[n])
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i1 = tx_data_h[n],
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io_prop = platform.get_pin_properties(pads.tx_data[n])
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i2 = tx_data_l[n],
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name = f"auto_{name}"
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o = pads.tx_data[n],
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clk = "auto_eth_tx_clk", # FIXME.
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tx_data_h.append(platform.add_iface_io(name + "_HI"))
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)
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tx_data_l.append(platform.add_iface_io(name + "_LO"))
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# FIXME: Integrate in EfinixDDROutputImpl.
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block = {
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"type" : "GPIO",
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"mode" : "OUTPUT",
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"name" : name,
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"location" : pad,
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"properties" : io_prop,
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"size" : 1,
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"out_reg" : "DDIO_RESYNC",
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"out_clk_pin" : "auto_eth_tx_clk",
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"is_inclk_inverted" : False,
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"drive_strength" : 4 # FIXME: Get it from constraints.
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}
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platform.toolchain.ifacewriter.blocks.append(block)
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platform.toolchain.excluded_ios.append(pads.tx_data)
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platform.toolchain.excluded_ios.append(pads.tx_data)
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# TX Ctl IOs.
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# TX Ctl IOs.
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# -----------
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# -----------
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name = platform.get_pin_name(pads.tx_ctl)
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if ddr_tx_ctl:
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pad = platform.get_pin_location(pads.tx_ctl)
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tx_ctl_h = Signal()
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io_prop = platform.get_pin_properties(pads.tx_ctl)
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tx_ctl_l = Signal()
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name = f"auto_{name}"
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self.specials += DDROutput(
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i1 = tx_ctl_h,
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tx_ctl_h = platform.add_iface_io(name + "_HI")
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i2 = tx_ctl_l,
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tx_ctl_l = platform.add_iface_io(name + "_LO")
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o = pads.tx_ctl,
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clk = "auto_eth_tx_clk", # FIXME.
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block = {
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)
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"type" : "GPIO",
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# FIXME: Integrate in EfinixDDROutputImpl.
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"mode" : "OUTPUT",
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platform.toolchain.excluded_ios.append(pads.tx_ctl)
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"name" : name,
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else:
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"location" : pad,
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self.sync.eth_tx += pads.tx_ctl.eq(sink.valid)
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"properties" : io_prop,
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"size" : 1,
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"out_reg" : "DDIO_RESYNC",
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"out_clk_pin" : "auto_eth_tx_clk",
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"is_inclk_inverted" : False,
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"drive_strength" : 4 # FIXME: Get it from constraints.
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}
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platform.toolchain.ifacewriter.blocks.append(block)
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platform.toolchain.excluded_ios.append(pads.tx_ctl)
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# Logic.
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# Logic.
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# ------
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# ------
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self.comb += sink.ready.eq(1)
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self.comb += sink.ready.eq(1)
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self.sync += [
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if ddr_tx_ctl:
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tx_ctl_h.eq(sink.valid),
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self.sync += [
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tx_ctl_l.eq(sink.valid),
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tx_ctl_h.eq(sink.valid),
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]
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tx_ctl_l.eq(sink.valid),
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]
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for n in range(4):
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for n in range(4):
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self.sync += [
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self.sync += [
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tx_data_h[n].eq(sink.data[n + 0]),
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tx_data_h[n].eq(sink.data[n + 0]),
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@ -102,29 +81,16 @@ class LiteEthPHYRGMIIRX(LiteXModule):
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# RX Data IOs.
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# RX Data IOs.
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# ------------
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# ------------
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rx_data_h = []
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rx_data_h = Signal(4)
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rx_data_l = []
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rx_data_l = Signal(4)
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for n in range(4):
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for n in range(4):
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name = platform.get_pin_name(pads.rx_data[n])
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self.specials += DDRInput(
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pad = platform.get_pin_location(pads.rx_data[n])
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i = pads.rx_data[n],
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io_prop = platform.get_pin_properties(pads.rx_data[n])
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o1 = rx_data_h[n],
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name = f"auto_{name}"
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o2 = rx_data_l[n],
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clk = "auto_eth_rx_clk", # FIXME.
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rx_data_h.append(platform.add_iface_io(name + "_HI"))
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)
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rx_data_l.append(platform.add_iface_io(name + "_LO"))
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# FIXME: Integrate in EfinixDDROutputImpl.
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block = {
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"type" : "GPIO",
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"mode" : "INPUT",
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"name" : name,
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"location" : pad,
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"properties" : io_prop,
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"size" : 1,
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"in_reg" : "DDIO_RESYNC",
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"in_clk_pin" : "auto_eth_rx_clk",
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"is_inclk_inverted" : False
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}
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platform.toolchain.ifacewriter.blocks.append(block)
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platform.toolchain.excluded_ios.append(pads.rx_data)
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platform.toolchain.excluded_ios.append(pads.rx_data)
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# RX Ctl IOs.
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# RX Ctl IOs.
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@ -12,6 +12,7 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.gen import *
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from litex.gen import *
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from litex.build.io import DDROutput, DDRInput
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from litex.build.generic_platform import *
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from litex.build.generic_platform import *
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from litex.soc.cores.clock import *
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from litex.soc.cores.clock import *
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@ -21,50 +22,53 @@ from liteeth.phy.common import *
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# LiteEth PHY RGMII TX -----------------------------------------------------------------------------
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# LiteEth PHY RGMII TX -----------------------------------------------------------------------------
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class LiteEthPHYRGMIITX(LiteXModule):
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class LiteEthPHYRGMIITX(LiteXModule):
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def __init__(self, platform, pads):
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def __init__(self, platform, pads, ddr_tx_ctl=False):
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self.sink = sink = stream.Endpoint(eth_phy_description(8))
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self.sink = sink = stream.Endpoint(eth_phy_description(8))
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# # #
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# # #
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# TX Data IOs.
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# TX Data IOs.
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# ------------
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# ------------
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tx_data_h = []
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tx_data_h = Signal(4)
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tx_data_l = []
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tx_data_l = Signal(4)
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for n in range(4):
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for n in range(4):
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name = platform.get_pin_name(pads.tx_data[n])
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self.specials += DDROutput(
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pad = platform.get_pin_location(pads.tx_data[n])
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i1 = tx_data_h[n],
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io_prop = platform.get_pin_properties(pads.tx_data[n])
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i2 = tx_data_l[n],
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name = f"auto_{name}"
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o = pads.tx_data[n],
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clk = "auto_eth_tx_clk", # FIXME.
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tx_data_h.append(platform.add_iface_io(name + "_HI"))
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)
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tx_data_l.append(platform.add_iface_io(name + "_LO"))
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# FIXME: Integrate in EfinixDDROutputImpl.
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block = {
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"type" : "GPIO",
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"mode" : "OUTPUT",
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"name" : name,
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"location" : pad,
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"properties" : io_prop,
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"size" : 1,
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"out_reg" : "DDIO_RESYNC",
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"out_clk_pin" : "auto_eth_tx_clk",
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"is_inclk_inverted" : False,
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"drive_strength" : 4 # FIXME: Get it from constraints.
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}
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platform.toolchain.ifacewriter.blocks.append(block)
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platform.toolchain.excluded_ios.append(pads.tx_data)
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platform.toolchain.excluded_ios.append(pads.tx_data)
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# TX Ctl IOs.
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# TX Ctl IOs.
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# -----------
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# -----------
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self.sync.eth_tx += pads.tx_ctl.eq(sink.valid)
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if ddr_tx_ctl:
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tx_ctl_h = Signal()
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tx_ctl_l = Signal()
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self.specials += DDROutput(
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i1 = tx_ctl_h,
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i2 = tx_ctl_l,
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o = pads.tx_ctl,
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clk = "auto_eth_tx_clk", # FIXME.
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)
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# FIXME: Integrate in EfinixDDROutputImpl.
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platform.toolchain.excluded_ios.append(pads.tx_ctl)
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else:
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self.sync.eth_tx += pads.tx_ctl.eq(sink.valid)
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# Logic.
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# Logic.
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# ------
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# ------
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self.comb += sink.ready.eq(1)
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self.comb += sink.ready.eq(1)
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if ddr_tx_ctl:
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self.sync += [
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tx_ctl_h.eq(sink.valid),
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tx_ctl_l.eq(sink.valid),
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]
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for n in range(4):
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for n in range(4):
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self.sync += [
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self.sync += [
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tx_data_h[n].eq(sink.data[n + 0]),
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tx_data_h[n].eq(sink.data[n + 0]),
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tx_data_l[n].eq(sink.data[n + 4])
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tx_data_l[n].eq(sink.data[n + 4]),
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]
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]
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# LiteEth PHY RGMII RX -----------------------------------------------------------------------------
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# LiteEth PHY RGMII RX -----------------------------------------------------------------------------
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@ -77,29 +81,16 @@ class LiteEthPHYRGMIIRX(LiteXModule):
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# RX Data IOs.
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# RX Data IOs.
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# ------------
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# ------------
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rx_data_h = []
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rx_data_h = Signal(4)
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rx_data_l = []
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rx_data_l = Signal(4)
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for n in range(4):
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for n in range(4):
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name = platform.get_pin_name(pads.rx_data[n])
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self.specials += DDRInput(
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pad = platform.get_pin_location(pads.rx_data[n])
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i = pads.rx_data[n],
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io_prop = platform.get_pin_properties(pads.rx_data[n])
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o1 = rx_data_h[n],
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name = f"auto_{name}"
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o2 = rx_data_l[n],
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clk = "auto_eth_rx_clk", # FIXME.
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rx_data_h.append(platform.add_iface_io(name + "_HI"))
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)
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rx_data_l.append(platform.add_iface_io(name + "_LO"))
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# FIXME: Integrate in EfinixDDROutputImpl.
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block = {
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"type" : "GPIO",
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"mode" : "INPUT",
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"name" : name,
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"location" : pad,
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"properties" : io_prop,
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"size" : 1,
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"in_reg" : "DDIO_RESYNC",
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"in_clk_pin" : "auto_eth_rx_clk",
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"is_inclk_inverted" : False
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}
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platform.toolchain.ifacewriter.blocks.append(block)
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platform.toolchain.excluded_ios.append(pads.rx_data)
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platform.toolchain.excluded_ios.append(pads.rx_data)
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# RX Ctl IOs.
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# RX Ctl IOs.
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@ -117,7 +108,7 @@ class LiteEthPHYRGMIIRX(LiteXModule):
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self.comb += last.eq(~pads.rx_ctl & rx_ctl_d)
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self.comb += last.eq(~pads.rx_ctl & rx_ctl_d)
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self.sync += [
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self.sync += [
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source.valid.eq(rx_ctl_d),
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source.valid.eq(rx_ctl_d),
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source.data.eq(rx_data)
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source.data.eq(rx_data),
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]
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]
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self.comb += source.last.eq(last)
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self.comb += source.last.eq(last)
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