diff --git a/liteeth/phy/trionrgmii.py b/liteeth/phy/trionrgmii.py
index edd5e8e..3ccc7c5 100644
--- a/liteeth/phy/trionrgmii.py
+++ b/liteeth/phy/trionrgmii.py
@@ -123,8 +123,9 @@ class LiteEthPHYRGMIICRG(LiteXModule):
 
         # Clk Domains.
         # ------------
-        self.cd_eth_rx = ClockDomain()
-        self.cd_eth_tx = ClockDomain()
+        self.cd_eth_rx         = ClockDomain()
+        self.cd_eth_tx         = ClockDomain()
+        self.cd_eth_tx_delayed = ClockDomain(reset_less=True)
 
         # RX Clk.
         # -------
@@ -136,17 +137,17 @@ class LiteEthPHYRGMIICRG(LiteXModule):
         # TX Clk.
         # -------
         self.specials += ClkOutput(
-            i = f"auto_eth{n}_tx_clk_delayed", # FIXME: Use Clk Signal.
+            i = ClockSignal("eth_tx_delayed"),
             o = clock_pads.tx
         )
 
         # TX PLL.
         # -------
         self.pll = pll = TRIONPLL(platform)
-        pll.register_clkin(None,          freq=125e6,           name=f"auto_eth{n}_rx_clk_in0") # FIXME: 0 is to match ClkInput
-        pll.create_clkout(self.cd_eth_rx, freq=125e6, phase=0, name=f"auto_eth{n}_rx_clk", with_reset=False, is_feedback=True)
-        pll.create_clkout(self.cd_eth_tx, freq=125e6, phase=0,  name=f"auto_eth{n}_tx_clk", with_reset=False)
-        pll.create_clkout(None,           freq=125e6, phase=45, name=f"auto_eth{n}_tx_clk_delayed")
+        pll.register_clkin(None,                  freq=125e6,           name=f"auto_eth{n}_rx_clk_in0") # FIXME: 0 is to match ClkInput
+        pll.create_clkout(self.cd_eth_rx,         freq=125e6, phase=0,  with_reset=False, is_feedback=True)
+        pll.create_clkout(self.cd_eth_tx,         freq=125e6, phase=0,  with_reset=False)
+        pll.create_clkout(self.cd_eth_tx_delayed, freq=125e6, phase=45)
 
         # Reset.
         # ------