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phy/trionrgmii.py: use ClockSignal for ClkOutput 'o', remove name parameter when a cd is used

This commit is contained in:
Gwenhael Goavec-Merou 2024-09-10 11:27:47 +02:00
parent 577a47222c
commit 88387cbd11
1 changed files with 8 additions and 7 deletions
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15
liteeth/phy/trionrgmii.py
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@ -123,8 +123,9 @@ class LiteEthPHYRGMIICRG(LiteXModule):
# Clk Domains.
# ------------
self.cd_eth_rx = ClockDomain()
self.cd_eth_tx = ClockDomain()
self.cd_eth_rx = ClockDomain()
self.cd_eth_tx = ClockDomain()
self.cd_eth_tx_delayed = ClockDomain(reset_less=True)
# RX Clk.
# -------
@ -136,17 +137,17 @@ class LiteEthPHYRGMIICRG(LiteXModule):
# TX Clk.
# -------
self.specials += ClkOutput(
i = f"auto_eth{n}_tx_clk_delayed", # FIXME: Use Clk Signal.
i = ClockSignal("eth_tx_delayed"),
o = clock_pads.tx
)
# TX PLL.
# -------
self.pll = pll = TRIONPLL(platform)
pll.register_clkin(None, freq=125e6, name=f"auto_eth{n}_rx_clk_in0") # FIXME: 0 is to match ClkInput
pll.create_clkout(self.cd_eth_rx, freq=125e6, phase=0, name=f"auto_eth{n}_rx_clk", with_reset=False, is_feedback=True)
pll.create_clkout(self.cd_eth_tx, freq=125e6, phase=0, name=f"auto_eth{n}_tx_clk", with_reset=False)
pll.create_clkout(None, freq=125e6, phase=45, name=f"auto_eth{n}_tx_clk_delayed")
pll.register_clkin(None, freq=125e6, name=f"auto_eth{n}_rx_clk_in0") # FIXME: 0 is to match ClkInput
pll.create_clkout(self.cd_eth_rx, freq=125e6, phase=0, with_reset=False, is_feedback=True)
pll.create_clkout(self.cd_eth_tx, freq=125e6, phase=0, with_reset=False)
pll.create_clkout(self.cd_eth_tx_delayed, freq=125e6, phase=45)
# Reset.
# ------