test: for now revert all simulation (we'll switch when missing feature of new simulator will be implemted)
This commit is contained in:
Florent Kermarrec
parent
57b70c640c
commit
886108eee9
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@ -1,6 +1,7 @@
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from migen import *
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from litex.soc.interconnect import wishbone
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from migen.fhdl.std import *
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from migen.bus import wishbone
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from migen.bus.transactions import *
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from migen.sim.generic import run_simulation
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from liteeth.common import *
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from liteeth.core.mac import LiteEthMAC
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@ -22,31 +23,36 @@ class TB(Module):
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self.submodules.mac = LiteEthMAC(self.phy_model, dw=8, with_preamble_crc=True)
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self.submodules.arp = LiteEthARP(self.mac, mac_address, ip_address, 100000)
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# use sys_clk for each clock_domain
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self.clock_domains.cd_eth_rx = ClockDomain()
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self.clock_domains.cd_eth_tx = ClockDomain()
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self.comb += [
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self.cd_eth_rx.clk.eq(ClockSignal()),
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self.cd_eth_rx.rst.eq(ResetSignal()),
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self.cd_eth_tx.clk.eq(ClockSignal()),
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self.cd_eth_tx.rst.eq(ResetSignal()),
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]
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def main_generator(dut):
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while (yield dut.arp.table.request.ack) != 1:
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yield dut.arp.table.request.stb.eq(1)
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yield dut.arp.table.request.ip_address.eq(0x12345678)
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def gen_simulation(self, selfp):
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selfp.cd_eth_rx.rst = 1
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selfp.cd_eth_tx.rst = 1
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yield
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yield dut.arp.table.request.stb.eq(0)
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while (yield dut.arp.table.response.stb) != 1:
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yield dut.arp.table.response.ack.eq(1)
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yield
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print("Received MAC : 0x{:12x}".format((yield dut.arp.table.response.mac_address)))
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selfp.cd_eth_rx.rst = 0
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selfp.cd_eth_tx.rst = 0
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for i in range(100):
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yield
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while selfp.arp.table.request.ack != 1:
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selfp.arp.table.request.stb = 1
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selfp.arp.table.request.ip_address = 0x12345678
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yield
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selfp.arp.table.request.stb = 0
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while selfp.arp.table.response.stb != 1:
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selfp.arp.table.response.ack = 1
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yield
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print("Received MAC : 0x{:12x}".format(selfp.arp.table.response.mac_address))
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# XXX: find a way to exit properly
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import sys
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sys.exit()
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if __name__ == "__main__":
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tb = TB()
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generators = {
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"sys" : [main_generator(tb)],
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"eth_tx": [tb.phy_model.phy_sink.generator(),
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tb.phy_model.generator()],
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"eth_rx": tb.phy_model.phy_source.generator()
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}
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clocks = {"sys": 10,
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"eth_rx": 10,
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"eth_tx": 10}
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run_simulation(tb, generators, clocks, vcd_name="sim.vcd")
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run_simulation(TB(), ncycles=2048, vcd_name="my.vcd", keep_files=True)
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@ -1,12 +1,12 @@
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import random
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import copy
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from migen import *
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from litex.soc.interconnect.stream import Sink, Source
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from migen.fhdl.std import *
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from migen.flow.actor import Sink, Source
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from migen.genlib.record import *
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from liteeth.common import *
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from copy import deepcopy
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def print_with_prefix(s, prefix=""):
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if not isinstance(s, str):
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@ -49,8 +49,8 @@ def comp(p1, p2):
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def check(p1, p2):
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p1 = deepcopy(p1)
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p2 = deepcopy(p2)
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p1 = copy.deepcopy(p1)
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p2 = copy.deepcopy(p2)
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if isinstance(p1, int):
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return 0, 1, int(p1 != p2)
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else:
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@ -94,7 +94,7 @@ class PacketStreamer(Module):
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self.packet.done = True
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def send(self, packet):
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packet = deepcopy(packet)
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packet = copy.deepcopy(packet)
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self.packets.append(packet)
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return packet
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@ -103,34 +103,32 @@ class PacketStreamer(Module):
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while not packet.done:
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yield
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def generator(self):
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while True:
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def do_simulation(self, selfp):
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if len(self.packets) and self.packet.done:
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self.packet = self.packets.pop(0)
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if not self.packet.ongoing and not self.packet.done:
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yield self.source.stb.eq(1)
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selfp.source.stb = 1
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if self.source.description.packetized:
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yield self.source.sop.eq(1)
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yield self.source.data.eq(self.packet.pop(0))
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selfp.source.sop = 1
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selfp.source.data = self.packet.pop(0)
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self.packet.ongoing = True
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elif (yield self.source.stb) == 1 and (yield self.source.ack) == 1:
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elif selfp.source.stb == 1 and selfp.source.ack == 1:
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if self.source.description.packetized:
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yield self.source.sop.eq(0)
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selfp.source.sop = 0
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if len(self.packet) == 1:
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yield self.source.eop.eq(1)
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selfp.source.eop = 1
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if self.last_be is not None:
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yield self.source.last_be.eq(self.last_be)
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selfp.source.last_be = self.last_be
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else:
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yield self.source.eop.eq(0)
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selfp.source.eop = 0
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if self.last_be is not None:
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yield self.source.last_be.eq(0)
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selfp.source.last_be = 0
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if len(self.packet) > 0:
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yield self.source.stb.eq(1)
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yield self.source.data.eq(self.packet.pop(0))
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selfp.source.stb = 1
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selfp.source.data = self.packet.pop(0)
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else:
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self.packet.done = True
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yield self.source.stb.eq(0)
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yield
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selfp.source.stb = 0
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class PacketLogger(Module):
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@ -146,21 +144,19 @@ class PacketLogger(Module):
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while not self.packet.done:
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yield
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def generator(self):
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while True:
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yield self.sink.ack.eq(1)
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if (yield self.sink.stb):
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def do_simulation(self, selfp):
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selfp.sink.ack = 1
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if selfp.sink.stb:
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if self.sink.description.packetized:
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if (yield self.sink.sop):
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if selfp.sink.sop:
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self.packet = Packet()
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self.packet.append((yield self.sink.data))
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self.packet.append(selfp.sink.data)
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else:
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self.packet.append((yield self.sink.data))
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if (yield self.sink.eop):
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self.packet.append(selfp.sink.data)
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if selfp.sink.eop:
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self.packet.done = True
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else:
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self.packet.append((yield self.sink.data))
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yield
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self.packet.append(selfp.sink.data)
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class AckRandomizer(Module):
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@ -170,22 +166,20 @@ class AckRandomizer(Module):
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self.sink = Sink(description)
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self.source = Source(description)
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self.ce = Signal(reset=1)
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self.run = Signal()
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self.comb += \
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If(self.ce,
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If(self.run,
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Record.connect(self.sink, self.source)
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).Else(
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self.source.stb.eq(0),
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self.sink.ack.eq(0),
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)
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def generator(self):
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while True:
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def do_simulation(self, selfp):
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n = randn(100)
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if n < self.level:
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yield self.ce.eq(0)
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selfp.run = 0
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else:
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yield self.ce.eq(1)
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yield
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selfp.run = 1
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@ -1,6 +1,7 @@
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from migen import *
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from litex.soc.interconnect import wishbone
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from migen.fhdl.std import *
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from migen.bus import wishbone
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from migen.bus.transactions import *
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from migen.sim.generic import run_simulation
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from liteeth.common import *
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from liteeth.core import LiteEthUDPIPCore
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@ -15,12 +16,12 @@ mac_address = 0x12345678abcd
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class TB(Module):
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def __init__(self):
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self.submodules.phy_model = phy.PHY(8, debug=True)
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self.submodules.mac_model = mac.MAC(self.phy_model, debug=True, loopback=False)
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self.submodules.arp_model = arp.ARP(self.mac_model, mac_address, ip_address, debug=True)
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self.submodules.ip_model = ip.IP(self.mac_model, mac_address, ip_address, debug=True, loopback=False)
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self.submodules.udp_model = udp.UDP(self.ip_model, ip_address, debug=True, loopback=False)
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self.submodules.etherbone_model = etherbone.Etherbone(self.udp_model, debug=True)
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self.submodules.phy_model = phy.PHY(8, debug=False)
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self.submodules.mac_model = mac.MAC(self.phy_model, debug=False, loopback=False)
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self.submodules.arp_model = arp.ARP(self.mac_model, mac_address, ip_address, debug=False)
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self.submodules.ip_model = ip.IP(self.mac_model, mac_address, ip_address, debug=False, loopback=False)
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self.submodules.udp_model = udp.UDP(self.ip_model, ip_address, debug=False, loopback=False)
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self.submodules.etherbone_model = etherbone.Etherbone(self.udp_model, debug=False)
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self.submodules.core = LiteEthUDPIPCore(self.phy_model, mac_address, ip_address, 100000)
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self.submodules.etherbone = LiteEthEtherbone(self.core.udp, 20000)
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@ -28,17 +29,35 @@ class TB(Module):
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self.submodules.sram = wishbone.SRAM(1024)
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self.submodules.interconnect = wishbone.InterconnectPointToPoint(self.etherbone.master.bus, self.sram.bus)
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# use sys_clk for each clock_domain
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self.clock_domains.cd_eth_rx = ClockDomain()
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self.clock_domains.cd_eth_tx = ClockDomain()
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self.comb += [
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self.cd_eth_rx.clk.eq(ClockSignal()),
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self.cd_eth_rx.rst.eq(ResetSignal()),
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self.cd_eth_tx.clk.eq(ClockSignal()),
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self.cd_eth_tx.rst.eq(ResetSignal()),
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]
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def gen_simulation(self, selfp):
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selfp.cd_eth_rx.rst = 1
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selfp.cd_eth_tx.rst = 1
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yield
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selfp.cd_eth_rx.rst = 0
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selfp.cd_eth_tx.rst = 0
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for i in range(100):
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yield
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def main_generator(dut):
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test_probe = True
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test_writes = False
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test_reads = False
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test_writes = True
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test_reads = True
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# test probe
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if test_probe:
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packet = etherbone.EtherbonePacket()
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packet.pf = 1
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dut.etherbone_model.send(packet)
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self.etherbone_model.send(packet)
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yield from self.etherbone_model.receive()
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print("probe: " + str(bool(self.etherbone_model.rx_packet.pr)))
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@ -92,23 +111,9 @@ def main_generator(dut):
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loopback_writes_datas = []
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loopback_writes_datas = self.etherbone_model.rx_packet.records.pop().writes.get_datas()
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# check resultss
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# check results
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s, l, e = check(writes_datas, loopback_writes_datas)
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print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e))
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# XXX: find a way to exit properly
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import sys
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sys.exit()
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if __name__ == "__main__":
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tb = TB()
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generators = {
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"sys" : [main_generator(tb)],
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"eth_tx": [tb.phy_model.phy_sink.generator(),
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tb.phy_model.generator()],
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"eth_rx": tb.phy_model.phy_source.generator()
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}
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clocks = {"sys": 10,
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"eth_rx": 10,
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"eth_tx": 10}
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run_simulation(tb, generators, clocks, vcd_name="sim.vcd")
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run_simulation(TB(), ncycles=4096, vcd_name="my.vcd", keep_files=True)
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@ -1,6 +1,7 @@
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from migen import *
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from litex.soc.interconnect import wishbone
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from migen.fhdl.std import *
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from migen.bus import wishbone
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from migen.bus.transactions import *
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from migen.sim.generic import run_simulation
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from liteeth.common import *
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from liteeth.core import LiteEthIPCore
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@ -26,31 +27,33 @@ class TB(Module):
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self.submodules.ip = LiteEthIPCore(self.phy_model, mac_address, ip_address, 100000)
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def main_generator(dut):
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# use sys_clk for each clock_domain
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self.clock_domains.cd_eth_rx = ClockDomain()
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self.clock_domains.cd_eth_tx = ClockDomain()
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self.comb += [
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self.cd_eth_rx.clk.eq(ClockSignal()),
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self.cd_eth_rx.rst.eq(ResetSignal()),
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self.cd_eth_tx.clk.eq(ClockSignal()),
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self.cd_eth_tx.rst.eq(ResetSignal()),
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]
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def gen_simulation(self, selfp):
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selfp.cd_eth_rx.rst = 1
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selfp.cd_eth_tx.rst = 1
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yield
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selfp.cd_eth_rx.rst = 0
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selfp.cd_eth_tx.rst = 0
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for i in range(100):
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yield
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packet = MACPacket(ping_request)
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packet.decode_remove_header()
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packet = IPPacket(packet)
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packet.decode()
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packet = ICMPPacket(packet)
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packet.decode()
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dut.icmp_model.send(packet)
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for i in range(256):
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yield
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# XXX: find a way to exit properly
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import sys
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sys.exit()
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self.icmp_model.send(packet)
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if __name__ == "__main__":
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tb = TB()
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generators = {
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"sys" : [main_generator(tb)],
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"eth_tx": [tb.phy_model.phy_sink.generator(),
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tb.phy_model.generator()],
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"eth_rx": tb.phy_model.phy_source.generator()
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}
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clocks = {"sys": 10,
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"eth_rx": 10,
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"eth_tx": 10}
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run_simulation(tb, generators, clocks, vcd_name="sim.vcd")
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run_simulation(TB(), ncycles=2048, vcd_name="my.vcd", keep_files=True)
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@ -1,6 +1,7 @@
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from migen import *
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from litex.soc.interconnect import wishbone
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from migen.fhdl.std import *
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from migen.bus import wishbone
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from migen.bus.transactions import *
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from migen.sim.generic import run_simulation
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from liteeth.common import *
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from liteeth.core import LiteEthIPCore
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@ -22,32 +23,38 @@ class TB(Module):
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self.submodules.ip = LiteEthIPCore(self.phy_model, mac_address, ip_address, 100000)
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self.ip_port = self.ip.ip.crossbar.get_port(udp_protocol)
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def main_generator(dut):
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while True:
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yield dut.ip_port.sink.stb.eq(1)
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yield dut.ip_port.sink.sop.eq(1)
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yield dut.ip_port.sink.eop.eq(1)
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yield dut.ip_port.sink.ip_address.eq(0x12345678)
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yield dut.ip_port.sink.protocol.eq(udp_protocol)
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# use sys_clk for each clock_domain
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self.clock_domains.cd_eth_rx = ClockDomain()
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self.clock_domains.cd_eth_tx = ClockDomain()
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self.comb += [
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self.cd_eth_rx.clk.eq(ClockSignal()),
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self.cd_eth_rx.rst.eq(ResetSignal()),
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self.cd_eth_tx.clk.eq(ClockSignal()),
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self.cd_eth_tx.rst.eq(ResetSignal()),
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]
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yield dut.ip_port.source.ack.eq(1)
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if (yield dut.ip_port.source.stb) == 1 and (yield dut.ip_port.source.sop) == 1:
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print("packet from IP 0x{:08x}".format((yield dut.ip_port.sink.ip_address)))
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# XXX: find a way to exit properly
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import sys
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sys.exit()
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def gen_simulation(self, selfp):
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selfp.cd_eth_rx.rst = 1
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selfp.cd_eth_tx.rst = 1
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yield
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selfp.cd_eth_rx.rst = 0
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selfp.cd_eth_tx.rst = 0
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for i in range(100):
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yield
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while True:
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selfp.ip_port.sink.stb = 1
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selfp.ip_port.sink.sop = 1
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selfp.ip_port.sink.eop = 1
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selfp.ip_port.sink.ip_address = 0x12345678
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selfp.ip_port.sink.protocol = udp_protocol
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selfp.ip_port.source.ack = 1
|
||||
if selfp.ip_port.source.stb == 1 and selfp.ip_port.source.sop == 1:
|
||||
print("packet from IP 0x{:08x}".format(selfp.ip_port.sink.ip_address))
|
||||
|
||||
yield
|
||||
|
||||
if __name__ == "__main__":
|
||||
tb = TB()
|
||||
generators = {
|
||||
"sys" : [main_generator(tb)],
|
||||
"eth_tx": [tb.phy_model.phy_sink.generator(),
|
||||
tb.phy_model.generator()],
|
||||
"eth_rx": tb.phy_model.phy_source.generator()
|
||||
}
|
||||
clocks = {"sys": 10,
|
||||
"eth_rx": 10,
|
||||
"eth_tx": 10}
|
||||
run_simulation(tb, generators, clocks, vcd_name="sim.vcd")
|
||||
run_simulation(TB(), ncycles=2048, vcd_name="my.vcd", keep_files=True)
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
from migen import *
|
||||
|
||||
from litex.soc.interconnect import wishbone
|
||||
from migen.fhdl.std import *
|
||||
from migen.bus import wishbone
|
||||
from migen.bus.transactions import *
|
||||
from migen.sim.generic import run_simulation
|
||||
|
||||
from liteeth.common import *
|
||||
from liteeth.core.mac.core import LiteEthMACCore
|
||||
|
|
@ -21,6 +22,16 @@ class TB(Module):
|
|||
self.submodules.logger_randomizer = AckRandomizer(eth_phy_description(8), level=50)
|
||||
self.submodules.logger = PacketLogger(eth_phy_description(8))
|
||||
|
||||
# use sys_clk for each clock_domain
|
||||
self.clock_domains.cd_eth_rx = ClockDomain()
|
||||
self.clock_domains.cd_eth_tx = ClockDomain()
|
||||
self.comb += [
|
||||
self.cd_eth_rx.clk.eq(ClockSignal()),
|
||||
self.cd_eth_rx.rst.eq(ResetSignal()),
|
||||
self.cd_eth_tx.clk.eq(ClockSignal()),
|
||||
self.cd_eth_tx.rst.eq(ResetSignal()),
|
||||
]
|
||||
|
||||
self.comb += [
|
||||
Record.connect(self.streamer.source, self.streamer_randomizer.sink),
|
||||
Record.connect(self.streamer_randomizer.source, self.core.sink),
|
||||
|
|
@ -28,38 +39,25 @@ class TB(Module):
|
|||
Record.connect(self.logger_randomizer.source, self.logger.sink)
|
||||
]
|
||||
|
||||
def gen_simulation(self, selfp):
|
||||
selfp.cd_eth_rx.rst = 1
|
||||
selfp.cd_eth_tx.rst = 1
|
||||
yield
|
||||
selfp.cd_eth_rx.rst = 0
|
||||
selfp.cd_eth_tx.rst = 0
|
||||
|
||||
def main_generator(dut):
|
||||
for i in range(2):
|
||||
for i in range(8):
|
||||
packet = mac.MACPacket([i for i in range(64)])
|
||||
packet.target_mac = 0x010203040506
|
||||
packet.sender_mac = 0x090A0B0C0C0D
|
||||
packet.ethernet_type = 0x0800
|
||||
packet.encode_header()
|
||||
dut.streamer.send(packet)
|
||||
yield from dut.logger.receive()
|
||||
yield from self.streamer.send(packet)
|
||||
yield from self.logger.receive()
|
||||
|
||||
# check results
|
||||
s, l, e = check(packet, dut.logger.packet)
|
||||
s, l, e = check(packet, self.logger.packet)
|
||||
print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e))
|
||||
|
||||
# XXX: find a way to exit properly
|
||||
import sys
|
||||
sys.exit()
|
||||
|
||||
if __name__ == "__main__":
|
||||
tb = TB()
|
||||
generators = {
|
||||
"sys" : [main_generator(tb),
|
||||
tb.streamer.generator(),
|
||||
tb.streamer_randomizer.generator(),
|
||||
tb.logger_randomizer.generator(),
|
||||
tb.logger.generator()],
|
||||
"eth_tx": [tb.phy_model.phy_sink.generator(),
|
||||
tb.phy_model.generator()],
|
||||
"eth_rx": tb.phy_model.phy_source.generator()
|
||||
}
|
||||
clocks = {"sys": 10,
|
||||
"eth_rx": 10,
|
||||
"eth_tx": 10}
|
||||
run_simulation(tb, generators, clocks, vcd_name="sim.vcd")
|
||||
run_simulation(TB(), ncycles=4000, vcd_name="my.vcd", keep_files=True)
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
from migen import *
|
||||
|
||||
from litex.soc.interconnect import wishbone
|
||||
from migen.fhdl.std import *
|
||||
from migen.bus import wishbone
|
||||
from migen.bus.transactions import *
|
||||
from migen.sim.generic import run_simulation
|
||||
|
||||
from liteeth.common import *
|
||||
from liteeth.core.mac import LiteEthMAC
|
||||
|
|
@ -15,30 +16,30 @@ class WishboneMaster:
|
|||
self.dat = 0
|
||||
|
||||
def write(self, adr, dat):
|
||||
yield self.obj.cyc.eq(1)
|
||||
yield self.obj.stb.eq(1)
|
||||
yield self.obj.adr.eq(adr)
|
||||
yield self.obj.we.eq(1)
|
||||
yield self.obj.sel.eq(0xf)
|
||||
yield self.obj.dat_w.eq(dat)
|
||||
while (yield self.obj.ack) == 0:
|
||||
self.obj.cyc = 1
|
||||
self.obj.stb = 1
|
||||
self.obj.adr = adr
|
||||
self.obj.we = 1
|
||||
self.obj.sel = 0xF
|
||||
self.obj.dat_w = dat
|
||||
while self.obj.ack == 0:
|
||||
yield
|
||||
yield self.obj.cyc.eq(0)
|
||||
yield self.obj.stb.eq(0)
|
||||
self.obj.cyc = 0
|
||||
self.obj.stb = 0
|
||||
yield
|
||||
|
||||
def read(self, adr):
|
||||
yield self.obj.cyc.eq(1)
|
||||
yield self.obj.stb.eq(1)
|
||||
yield self.obj.adr.eq(adr)
|
||||
yield self.obj.we.eq(0)
|
||||
yield self.obj.sel.eq(0xf)
|
||||
yield self.obj.dat_w.eq(0)
|
||||
while (yield self.obj.ack) == 0:
|
||||
self.obj.cyc = 1
|
||||
self.obj.stb = 1
|
||||
self.obj.adr = adr
|
||||
self.obj.we = 0
|
||||
self.obj.sel = 0xF
|
||||
self.obj.dat_w = 0
|
||||
while self.obj.ack == 0:
|
||||
yield
|
||||
yield self.dat.eq(self.obj.dat_r)
|
||||
yield self.obj.cyc.eq(0)
|
||||
yield self.obj.stb.eq(0)
|
||||
self.dat = self.obj.dat_r
|
||||
self.obj.cyc = 0
|
||||
self.obj.stb = 0
|
||||
yield
|
||||
|
||||
|
||||
|
|
@ -47,21 +48,21 @@ class SRAMReaderDriver:
|
|||
self.obj = obj
|
||||
|
||||
def start(self, slot, length):
|
||||
yield self.obj._slot.storage.eq(slot)
|
||||
yield self.obj._length.storage.eq(length)
|
||||
yield self.obj._start.re.eq(1)
|
||||
self.obj._slot.storage = slot
|
||||
self.obj._length.storage = length
|
||||
self.obj._start.re = 1
|
||||
yield
|
||||
yield self.obj._start.re.eq(0)
|
||||
self.obj._start.re = 0
|
||||
yield
|
||||
|
||||
def wait_done(self):
|
||||
while (yield self.obj.ev.done.pending) == 0:
|
||||
while self.obj.ev.done.pending == 0:
|
||||
yield
|
||||
|
||||
def clear_done(self):
|
||||
yield self.obj.ev.done.clear.eq(1)
|
||||
self.obj.ev.done.clear = 1
|
||||
yield
|
||||
yield self.obj.ev.done.clear.eq(0)
|
||||
self.obj.ev.done.clear = 0
|
||||
yield
|
||||
|
||||
|
||||
|
|
@ -70,27 +71,42 @@ class SRAMWriterDriver:
|
|||
self.obj = obj
|
||||
|
||||
def wait_available(self):
|
||||
while (yield self.obj.ev.available.pending) == 0:
|
||||
while self.obj.ev.available.pending == 0:
|
||||
yield
|
||||
|
||||
def clear_available(self):
|
||||
yield self.obj.ev.available.clear.eq(1)
|
||||
self.obj.ev.available.clear = 1
|
||||
yield
|
||||
yield self.obj.ev.available.clear.eq(0)
|
||||
self.obj.ev.available.clear = 0
|
||||
yield
|
||||
|
||||
|
||||
class TB(Module):
|
||||
def __init__(self):
|
||||
self.submodules.phy_model = phy.PHY(8, debug=True)
|
||||
self.submodules.mac_model = mac.MAC(self.phy_model, debug=True, loopback=True)
|
||||
self.submodules.phy_model = phy.PHY(8, debug=False)
|
||||
self.submodules.mac_model = mac.MAC(self.phy_model, debug=False, loopback=True)
|
||||
self.submodules.ethmac = LiteEthMAC(phy=self.phy_model, dw=32, interface="wishbone", with_preamble_crc=True)
|
||||
|
||||
# use sys_clk for each clock_domain
|
||||
self.clock_domains.cd_eth_rx = ClockDomain()
|
||||
self.clock_domains.cd_eth_tx = ClockDomain()
|
||||
self.comb += [
|
||||
self.cd_eth_rx.clk.eq(ClockSignal()),
|
||||
self.cd_eth_rx.rst.eq(ResetSignal()),
|
||||
self.cd_eth_tx.clk.eq(ClockSignal()),
|
||||
self.cd_eth_tx.rst.eq(ResetSignal()),
|
||||
]
|
||||
|
||||
def main_generator(dut):
|
||||
wishbone_master = WishboneMaster(dut.ethmac.bus)
|
||||
sram_reader_driver = SRAMReaderDriver(dut.ethmac.interface.sram.reader)
|
||||
sram_writer_driver = SRAMWriterDriver(dut.ethmac.interface.sram.writer)
|
||||
def gen_simulation(self, selfp):
|
||||
selfp.cd_eth_rx.rst = 1
|
||||
selfp.cd_eth_tx.rst = 1
|
||||
yield
|
||||
selfp.cd_eth_rx.rst = 0
|
||||
selfp.cd_eth_tx.rst = 0
|
||||
|
||||
wishbone_master = WishboneMaster(selfp.ethmac.bus)
|
||||
sram_reader_driver = SRAMReaderDriver(selfp.ethmac.interface.sram.reader)
|
||||
sram_writer_driver = SRAMWriterDriver(selfp.ethmac.interface.sram.writer)
|
||||
|
||||
sram_writer_slots_offset = [0x000, 0x200]
|
||||
sram_reader_slots_offset = [0x400, 0x600]
|
||||
|
|
@ -102,8 +118,6 @@ def main_generator(dut):
|
|||
errors = 0
|
||||
|
||||
while True:
|
||||
for i in range(20):
|
||||
yield
|
||||
for slot in range(2):
|
||||
print("slot {}: ".format(slot), end="")
|
||||
# fill tx memory
|
||||
|
|
@ -111,39 +125,25 @@ def main_generator(dut):
|
|||
dat = int.from_bytes(tx_payload[4*i:4*(i+1)], "big")
|
||||
yield from wishbone_master.write(sram_reader_slots_offset[slot]+i, dat)
|
||||
|
||||
# XXX: find a way to exit properly
|
||||
import sys
|
||||
sys.exit()
|
||||
# send tx payload & wait
|
||||
yield from sram_reader_driver.start(slot, length)
|
||||
yield from sram_reader_driver.wait_done()
|
||||
yield from sram_reader_driver.clear_done()
|
||||
|
||||
# # send tx payload & wait
|
||||
# yield from sram_reader_driver.start(slot, length)
|
||||
# yield from sram_reader_driver.wait_done()
|
||||
# yield from sram_reader_driver.clear_done()
|
||||
#
|
||||
# # wait rx
|
||||
# yield from sram_writer_driver.wait_available()
|
||||
# yield from sram_writer_driver.clear_available()
|
||||
#
|
||||
# # get rx payload (loopback on PHY Model)
|
||||
# rx_payload = []
|
||||
# for i in range(length//4+1):
|
||||
# yield from wishbone_master.read(sram_writer_slots_offset[slot]+i)
|
||||
# dat = wishbone_master.dat
|
||||
# rx_payload += list(dat.to_bytes(4, byteorder='big'))
|
||||
#
|
||||
# # check results
|
||||
# s, l, e = check(tx_payload[:length], rx_payload[:min(length, len(rx_payload))])
|
||||
# print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e))
|
||||
# wait rx
|
||||
yield from sram_writer_driver.wait_available()
|
||||
yield from sram_writer_driver.clear_available()
|
||||
|
||||
# get rx payload (loopback on PHY Model)
|
||||
rx_payload = []
|
||||
for i in range(length//4+1):
|
||||
yield from wishbone_master.read(sram_writer_slots_offset[slot]+i)
|
||||
dat = wishbone_master.dat
|
||||
rx_payload += list(dat.to_bytes(4, byteorder='big'))
|
||||
|
||||
# check results
|
||||
s, l, e = check(tx_payload[:length], rx_payload[:min(length, len(rx_payload))])
|
||||
print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e))
|
||||
|
||||
if __name__ == "__main__":
|
||||
tb = TB()
|
||||
generators = {
|
||||
"sys" : main_generator(tb),
|
||||
"eth_tx": [tb.phy_model.phy_sink.generator(),
|
||||
tb.phy_model.generator()],
|
||||
"eth_rx": tb.phy_model.phy_source.generator()
|
||||
}
|
||||
clocks = {"sys": 10,
|
||||
"eth_rx": 10,
|
||||
"eth_tx": 10}
|
||||
run_simulation(tb, generators, clocks, vcd_name="sim.vcd")
|
||||
run_simulation(TB(), ncycles=3000, vcd_name="my.vcd", keep_files=True)
|
||||
|
|
|
|||
|
|
@ -54,7 +54,7 @@ class PHY(Module):
|
|||
print_phy(r)
|
||||
self.packet = self.phy_sink.packet
|
||||
|
||||
def generator(self):
|
||||
def gen_simulation(self, selfp):
|
||||
while True:
|
||||
yield from self.receive()
|
||||
if self.mac_callback is not None:
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
from migen import *
|
||||
|
||||
from litex.soc.interconnect import wishbone
|
||||
from migen.fhdl.std import *
|
||||
from migen.bus import wishbone
|
||||
from migen.bus.transactions import *
|
||||
from migen.sim.generic import run_simulation
|
||||
|
||||
from liteeth.common import *
|
||||
from liteeth.core import LiteEthUDPIPCore
|
||||
|
|
@ -34,30 +35,37 @@ class TB(Module):
|
|||
Record.connect(udp_port.source, self.logger.sink)
|
||||
]
|
||||
|
||||
def main_generator(dut):
|
||||
packet = Packet([i for i in range(64//(dut.dw//8))])
|
||||
dut.streamer.send(packet)
|
||||
yield from dut.logger.receive()
|
||||
# use sys_clk for each clock_domain
|
||||
self.clock_domains.cd_eth_rx = ClockDomain()
|
||||
self.clock_domains.cd_eth_tx = ClockDomain()
|
||||
self.comb += [
|
||||
self.cd_eth_rx.clk.eq(ClockSignal()),
|
||||
self.cd_eth_rx.rst.eq(ResetSignal()),
|
||||
self.cd_eth_tx.clk.eq(ClockSignal()),
|
||||
self.cd_eth_tx.rst.eq(ResetSignal()),
|
||||
]
|
||||
|
||||
def gen_simulation(self, selfp):
|
||||
selfp.cd_eth_rx.rst = 1
|
||||
selfp.cd_eth_tx.rst = 1
|
||||
yield
|
||||
selfp.cd_eth_rx.rst = 0
|
||||
selfp.cd_eth_tx.rst = 0
|
||||
|
||||
for i in range(100):
|
||||
yield
|
||||
|
||||
while True:
|
||||
packet = Packet([i for i in range(64//(self.dw//8))])
|
||||
yield from self.streamer.send(packet)
|
||||
yield from self.logger.receive()
|
||||
|
||||
# check results
|
||||
s, l, e = check(packet, dut.logger.packet)
|
||||
s, l, e = check(packet, self.logger.packet)
|
||||
print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e))
|
||||
|
||||
# XXX: find a way to exit properly
|
||||
import sys
|
||||
sys.exit()
|
||||
|
||||
if __name__ == "__main__":
|
||||
tb = TB(8)
|
||||
generators = {
|
||||
"sys" : [main_generator(tb),
|
||||
tb.streamer.generator(),
|
||||
tb.logger.generator()],
|
||||
"eth_tx": [tb.phy_model.phy_sink.generator(),
|
||||
tb.phy_model.generator()],
|
||||
"eth_rx": tb.phy_model.phy_source.generator()
|
||||
}
|
||||
clocks = {"sys": 10,
|
||||
"eth_rx": 10,
|
||||
"eth_tx": 10}
|
||||
run_simulation(tb, generators, clocks, vcd_name="sim.vcd")
|
||||
run_simulation(TB(8), ncycles=2048, vcd_name="my.vcd", keep_files=True)
|
||||
run_simulation(TB(16), ncycles=2048, vcd_name="my.vcd", keep_files=True)
|
||||
run_simulation(TB(32), ncycles=2048, vcd_name="my.vcd", keep_files=True)
|
||||
|
|
|
|||
Loading…
Reference in New Issue