From cd413c5c20215225b002e46862a283a87814d7c5 Mon Sep 17 00:00:00 2001 From: Vamsi K Vytla Date: Mon, 27 Jan 2020 10:32:38 -0800 Subject: [PATCH 1/2] phy/usrgmii.py: IDELAYE3 requires EN_VTC to be enabled for fixed mode time delay. This eliminates implementation time CRITICAL WARNINGs and ensures generating a bitfile. --- liteeth/phy/usrgmii.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/liteeth/phy/usrgmii.py b/liteeth/phy/usrgmii.py index c7e8d01..61d4099 100644 --- a/liteeth/phy/usrgmii.py +++ b/liteeth/phy/usrgmii.py @@ -77,7 +77,7 @@ class LiteEthPHYRGMIIRX(Module): i_CNTVALUEIN=0, i_IDATAIN=rx_ctl_ibuf, i_RST=0, - i_EN_VTC=0, + i_EN_VTC=1, o_DATAOUT=rx_ctl_idelay), Instance("IDDRE1", p_DDR_CLK_EDGE="SAME_EDGE_PIPELINED", @@ -110,7 +110,7 @@ class LiteEthPHYRGMIIRX(Module): i_CNTVALUEIN=0, i_IDATAIN=rx_data_ibuf[i], i_RST=0, - i_EN_VTC=0, + i_EN_VTC=1, o_DATAOUT=rx_data_idelay[i]), Instance("IDDRE1", p_DDR_CLK_EDGE="SAME_EDGE_PIPELINED", From 8ecaaf0546b1431e134b8ff992dd47db6ef8867f Mon Sep 17 00:00:00 2001 From: Vamsi K Vytla Date: Mon, 27 Jan 2020 12:52:10 -0800 Subject: [PATCH 2/2] phy/{s7,us}rgmii.py: Recent modification that adds S7PLL that in return adds an AsyncResetSynchronizer inside XilinxClocking. This actually creates a multi-driven net because there is another AsyncResetSync* being added in the Phys. This change instantiates the PLL without a reset for now, leaving the CD reset intact. --- liteeth/phy/s7rgmii.py | 2 +- liteeth/phy/usrgmii.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/liteeth/phy/s7rgmii.py b/liteeth/phy/s7rgmii.py index 25cf00b..9c41889 100644 --- a/liteeth/phy/s7rgmii.py +++ b/liteeth/phy/s7rgmii.py @@ -118,7 +118,7 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR): from litex.soc.cores.clock import S7PLL self.submodules.pll = pll = S7PLL() pll.register_clkin(ClockSignal("eth_rx"), 125e6) - pll.create_clkout(self.cd_eth_tx, 125e6) + pll.create_clkout(self.cd_eth_tx, 125e6, with_reset=False) pll.create_clkout(self.cd_eth_tx_delayed, 125e6, phase=tx_phase) eth_tx_clk_obuf = Signal() diff --git a/liteeth/phy/usrgmii.py b/liteeth/phy/usrgmii.py index 61d4099..524200c 100644 --- a/liteeth/phy/usrgmii.py +++ b/liteeth/phy/usrgmii.py @@ -159,7 +159,7 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR): from litex.soc.cores.clock import USPLL self.submodules.pll = pll = USPLL() pll.register_clkin(ClockSignal("eth_rx"), 125e6) - pll.create_clkout(self.cd_eth_tx, 125e6) + pll.create_clkout(self.cd_eth_tx, 125e6, with_reset=False) pll.create_clkout(self.cd_eth_tx_delayed, 125e6, phase=tx_phase) eth_tx_clk_obuf = Signal()