diff --git a/liteeth/core/__init__.py b/liteeth/core/__init__.py index 9a6f593..f51ad11 100644 --- a/liteeth/core/__init__.py +++ b/liteeth/core/__init__.py @@ -5,11 +5,11 @@ # Copyright (c) 2023 LumiGuide Fietsdetectie B.V. # SPDX-License-Identifier: BSD-2-Clause -from liteeth.common import * -from liteeth.mac import LiteEthMAC -from liteeth.core.arp import LiteEthARP -from liteeth.core.ip import LiteEthIP -from liteeth.core.udp import LiteEthUDP +from liteeth.common import * +from liteeth.mac import LiteEthMAC +from liteeth.core.arp import LiteEthARP +from liteeth.core.ip import LiteEthIP +from liteeth.core.udp import LiteEthUDP from liteeth.core.icmp import LiteEthICMP # IP Core ------------------------------------------------------------------------------------------ @@ -22,7 +22,8 @@ class LiteEthIPCore(Module, AutoCSR): tx_cdc_depth = 32, tx_cdc_buffered = False, rx_cdc_depth = 32, - rx_cdc_buffered = False): + rx_cdc_buffered = False, + ): # Parameters. # ----------- ip_address = convert_ip(ip_address) @@ -30,15 +31,15 @@ class LiteEthIPCore(Module, AutoCSR): # MAC. # ---- self.submodules.mac = LiteEthMAC( - phy = phy, - dw = dw, - interface = "crossbar", + phy = phy, + dw = dw, + interface = "crossbar", with_preamble_crc = True, with_sys_datapath = with_sys_datapath, - tx_cdc_depth = tx_cdc_depth, - tx_cdc_buffered = tx_cdc_buffered, - rx_cdc_depth = rx_cdc_depth, - rx_cdc_buffered = rx_cdc_buffered + tx_cdc_depth = tx_cdc_depth, + tx_cdc_buffered = tx_cdc_buffered, + rx_cdc_depth = rx_cdc_depth, + rx_cdc_buffered = rx_cdc_buffered ) # ARP. @@ -80,7 +81,8 @@ class LiteEthUDPIPCore(LiteEthIPCore): tx_cdc_depth = 32, tx_cdc_buffered = False, rx_cdc_depth = 32, - rx_cdc_buffered = False): + rx_cdc_buffered = False, + ): # Parameters. # ----------- ip_address = convert_ip(ip_address) @@ -88,18 +90,18 @@ class LiteEthUDPIPCore(LiteEthIPCore): # Core: MAC + ARP + IP + (ICMP). # ------------------------------ LiteEthIPCore.__init__(self, - phy = phy, - mac_address = mac_address, - ip_address = ip_address, - clk_freq = clk_freq, - with_icmp = with_icmp, - dw = dw, + phy = phy, + mac_address = mac_address, + ip_address = ip_address, + clk_freq = clk_freq, + with_icmp = with_icmp, + dw = dw, with_ip_broadcast = with_ip_broadcast, with_sys_datapath = with_sys_datapath, tx_cdc_depth = tx_cdc_depth, tx_cdc_buffered = tx_cdc_buffered, rx_cdc_depth = rx_cdc_depth, - rx_cdc_buffered = rx_cdc_buffered + rx_cdc_buffered = rx_cdc_buffered, ) # UDP. # ---- diff --git a/liteeth/gen.py b/liteeth/gen.py index 9cadb4d..8542a60 100755 --- a/liteeth/gen.py +++ b/liteeth/gen.py @@ -303,10 +303,10 @@ class MACCore(PHYCore): nrxslots = nrxslots, ntxslots = ntxslots, full_memory_we = core_config.get("full_memory_we", False), - tx_cdc_depth = tx_cdc_depth - tx_cdc_buffered = tx_cdc_buffered - rx_cdc_depth = rx_cdc_depth - rx_cdc_buffered = rx_cdc_buffered + tx_cdc_depth = tx_cdc_depth, + tx_cdc_buffered = tx_cdc_buffered, + rx_cdc_depth = rx_cdc_depth, + rx_cdc_buffered = rx_cdc_buffered, ) if bus_standard == "wishbone": @@ -364,16 +364,15 @@ class UDPCore(PHYCore): # Core ------------------------------------------------------------------------------------- data_width = core_config.get("data_width", 8) self.submodules.core = LiteEthUDPIPCore(self.ethphy, - mac_address = mac_address, - ip_address = ip_address, - clk_freq = core_config["clk_freq"], - dw = data_width, + mac_address = mac_address, + ip_address = ip_address, + clk_freq = core_config["clk_freq"], + dw = data_width, with_sys_datapath = (data_width == 32), - tx_cdc_depth = tx_cdc_depth - tx_cdc_buffered = tx_cdc_buffered - rx_cdc_depth = rx_cdc_depth - rx_cdc_buffered = rx_cdc_buffered - + tx_cdc_depth = tx_cdc_depth, + tx_cdc_buffered = tx_cdc_buffered, + rx_cdc_depth = rx_cdc_depth, + rx_cdc_buffered = rx_cdc_buffered, ) # DHCP ------------------------------------------------------------------------------------- diff --git a/liteeth/mac/__init__.py b/liteeth/mac/__init__.py index 031a966..e451904 100644 --- a/liteeth/mac/__init__.py +++ b/liteeth/mac/__init__.py @@ -14,20 +14,22 @@ from liteeth.mac.wishbone import LiteEthMACWishboneInterface class LiteEthMAC(Module, AutoCSR): def __init__(self, phy, dw, - interface = "crossbar", - endianness = "big", - with_preamble_crc = True, - nrxslots = 2, rxslots_read_only = True, - ntxslots = 2, txslots_write_only = False, - hw_mac = None, - timestamp = None, - full_memory_we = False, - with_sys_datapath = False, - tx_cdc_depth = 32, - tx_cdc_buffered = False, - rx_cdc_depth = 32, - rx_cdc_buffered = False): - + interface = "crossbar", + endianness = "big", + with_preamble_crc = True, + nrxslots = 2, + rxslots_read_only = True, + ntxslots = 2, + txslots_write_only = False, + hw_mac = None, + timestamp = None, + full_memory_we = False, + with_sys_datapath = False, + tx_cdc_depth = 32, + tx_cdc_buffered = False, + rx_cdc_depth = 32, + rx_cdc_buffered = False, + ): assert dw%8 == 0 assert interface in ["crossbar", "wishbone", "hybrid"] assert endianness in ["big", "little"] @@ -40,7 +42,7 @@ class LiteEthMAC(Module, AutoCSR): tx_cdc_depth = tx_cdc_depth, tx_cdc_buffered = tx_cdc_buffered, rx_cdc_depth = rx_cdc_depth, - rx_cdc_buffered = rx_cdc_buffered + rx_cdc_buffered = rx_cdc_buffered, ) self.csrs = [] if interface == "crossbar": diff --git a/liteeth/mac/core.py b/liteeth/mac/core.py index 203c79f..fd782f4 100644 --- a/liteeth/mac/core.py +++ b/liteeth/mac/core.py @@ -20,14 +20,14 @@ from litex.soc.interconnect.stream import BufferizeEndpoints, DIR_SOURCE, DIR_SI class LiteEthMACCore(Module, AutoCSR): def __init__(self, phy, dw, - with_sys_datapath = False, - with_preamble_crc = True, - with_padding = True, - tx_cdc_depth = 32, - tx_cdc_buffered = False, - rx_cdc_depth = 32, - rx_cdc_buffered = False, - ): + with_sys_datapath = False, + with_preamble_crc = True, + with_padding = True, + tx_cdc_depth = 32, + tx_cdc_buffered = False, + rx_cdc_depth = 32, + rx_cdc_buffered = False, + ): # Endpoints. self.sink = stream.Endpoint(eth_phy_description(dw)) @@ -61,11 +61,11 @@ class LiteEthMACCore(Module, AutoCSR): def add_cdc(self): tx_cdc = stream.ClockDomainCrossing(eth_phy_description(core_dw), - cd_from = "sys", - cd_to = "eth_tx", - depth = tx_cdc_depth, - buffered = tx_cdc_buffered - ) + cd_from = "sys", + cd_to = "eth_tx", + depth = tx_cdc_depth, + buffered = tx_cdc_buffered, + ) self.submodules += tx_cdc self.pipeline.append(tx_cdc) @@ -132,7 +132,7 @@ class LiteEthMACCore(Module, AutoCSR): tx_datapath.add_converter() if core_dw != 8: tx_datapath.add_last_be() - # Gap insertion has to occurr in phy tx domain to ensure gap is correctly maintained + # Gap insertion has to occurr in phy tx domain to ensure gap is correctly maintained. if not getattr(phy, "integrated_ifg_inserter", False): tx_datapath.add_gap() tx_datapath.pipeline.append(phy) @@ -192,10 +192,10 @@ class LiteEthMACCore(Module, AutoCSR): def add_cdc(self): rx_cdc = stream.ClockDomainCrossing(eth_phy_description(core_dw), - cd_from = "eth_rx", - cd_to = "sys", - depth = rx_cdc_depth, - buffered = rx_cdc_buffered + cd_from = "eth_rx", + cd_to = "sys", + depth = rx_cdc_depth, + buffered = rx_cdc_buffered, ) self.submodules += rx_cdc self.pipeline.append(rx_cdc)