mac/sram: LiteEthMACSRAMReader: force READ_FIRST for mems ports (fix tx packet corruption for efinix trion/titanium)
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@ -282,7 +282,7 @@ class LiteEthMACSRAMReader(Module, AutoCSR):
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ports = [None]*nslots
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for n in range(nslots):
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mems[n] = Memory(dw, depth)
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ports[n] = mems[n].get_port(has_re=True)
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ports[n] = mems[n].get_port(has_re=True, mode=READ_FIRST)
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self.specials += ports[n]
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self.mems = mems
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