From 8e1185711ba3def1949fb5942aad4a9dc6e02c77 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 22 Jun 2020 14:36:44 +0200
Subject: [PATCH] common: remove Port.connect and use 2 separate
 Record.connect.

---
 examples/targets/udp.py                     | 3 ++-
 examples/targets/udp_loopback/versa_ecp5.py | 4 ++--
 liteeth/common.py                           | 7 -------
 liteeth/mac/__init__.py                     | 3 ++-
 4 files changed, 6 insertions(+), 11 deletions(-)

diff --git a/examples/targets/udp.py b/examples/targets/udp.py
index 2b17150..973cf3d 100644
--- a/examples/targets/udp.py
+++ b/examples/targets/udp.py
@@ -26,7 +26,8 @@ class UDPSoC(BaseSoC):
             self.submodules += buf
         else:
             setattr(self.submodules, name, buf)
-        self.comb += Port.connect(port, buf)
+        self.comb += port.source.connect(buf.sink)
+        self.comb += buf.source.connect(port.sink)
 
 # UDPSoCDevel --------------------------------------------------------------------------------------
 
diff --git a/examples/targets/udp_loopback/versa_ecp5.py b/examples/targets/udp_loopback/versa_ecp5.py
index 57d10ef..a63101b 100755
--- a/examples/targets/udp_loopback/versa_ecp5.py
+++ b/examples/targets/udp_loopback/versa_ecp5.py
@@ -82,8 +82,8 @@ class UDPLoopback(SoCMini):
             self.submodules += buf
         else:
             setattr(self.submodules, name, buf)
-        self.comb += Port.connect(port, buf)
-
+        self.comb += port.source.connect(buf.sink)
+        self.comb += buf.source.connect(port.sink)
 
 # Load ---------------------------------------------------------------------------------------------
 def load():
diff --git a/liteeth/common.py b/liteeth/common.py
index 458e859..d5207a3 100644
--- a/liteeth/common.py
+++ b/liteeth/common.py
@@ -14,13 +14,6 @@ from litex.soc.interconnect.csr import *
 from litex.soc.interconnect.packet import Header, HeaderField
 
 
-class Port:
-    def connect(self, port):
-        r = [self.source.connect(port.sink),
-             port.source.connect(self.sink)]
-        return r
-
-
 eth_mtu = 1530
 eth_min_len = 46
 eth_interpacket_gap = 12
diff --git a/liteeth/mac/__init__.py b/liteeth/mac/__init__.py
index 05b5a55..39fd5e7 100644
--- a/liteeth/mac/__init__.py
+++ b/liteeth/mac/__init__.py
@@ -41,7 +41,8 @@ class LiteEthMAC(Module, AutoCSR):
                 self.submodules.mac_crossbar = LiteEthMACCoreCrossbar(self.core, self.crossbar, self.interface, dw, endianness, hw_mac)
             else:
                 assert dw == 32
-                self.comb += Port.connect(self.interface, self.core)
+                self.comb += self.interface.source.connect(self.core.sink)
+                self.comb += self.core.source.connect(self.interface.sink)
 
     def get_csrs(self):
         return self.csrs