From 8fb0dae18a0c9ae35ca3d94dd54bd03aa6873565 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 17 Jan 2020 08:57:52 +0100 Subject: [PATCH] phy/s6rgmii: improve presentation --- liteeth/phy/s6rgmii.py | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/liteeth/phy/s6rgmii.py b/liteeth/phy/s6rgmii.py index 10c62b7..57406e6 100644 --- a/liteeth/phy/s6rgmii.py +++ b/liteeth/phy/s6rgmii.py @@ -16,7 +16,7 @@ class LiteEthPHYRGMIITX(Module): # # # - tx_ctl_obuf = Signal() + tx_ctl_obuf = Signal() tx_data_obuf = Signal(4) self.specials += [ @@ -89,14 +89,14 @@ class LiteEthPHYRGMIIRX(Module): # # # - rx_ctl_ibuf = Signal() - rx_ctl_idelay = Signal() - rx_ctl = Signal() - rx_ctl_reg = Signal() - rx_data_ibuf = Signal(4) + rx_ctl_ibuf = Signal() + rx_ctl_idelay = Signal() + rx_ctl = Signal() + rx_ctl_reg = Signal() + rx_data_ibuf = Signal(4) rx_data_idelay = Signal(4) - rx_data = Signal(8) - rx_data_reg = Signal(8) + rx_data = Signal(8) + rx_data_reg = Signal(8) self.specials += [ Instance("IBUF", i_I=pads.rx_ctl, o_O=rx_ctl_ibuf), @@ -243,8 +243,8 @@ class LiteEthPHYRGMII(Module, AutoCSR): def __init__(self, clock_pads, pads, with_hw_init_reset=True): self.dw = 8 self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads, pads, with_hw_init_reset) - self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(pads)) - self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRGMIIRX(pads)) + self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(pads)) + self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRGMIIRX(pads)) self.sink, self.source = self.tx.sink, self.rx.source if hasattr(pads, "mdc"):