From 20af2bf2014c69b7e4f0c942dd557ab6854a76bf Mon Sep 17 00:00:00 2001 From: Felix Held Date: Sat, 13 Jan 2018 13:23:18 +1100 Subject: [PATCH] Fix all remaining indentation issues in python code I ran a script that shouldn't have missed any tab in the python source files. --- liteeth/phy/gmii.py | 14 +++++++------- setup.py | 30 +++++++++++++++--------------- 2 files changed, 22 insertions(+), 22 deletions(-) diff --git a/liteeth/phy/gmii.py b/liteeth/phy/gmii.py index 0616b08..b0a2486 100644 --- a/liteeth/phy/gmii.py +++ b/liteeth/phy/gmii.py @@ -55,14 +55,14 @@ class LiteEthPHYGMIICRG(Module, AutoCSR): # MII: Use PHY clock_pads.tx as eth_tx_clk, do not drive clock_pads.gtx self.specials += DDROutput(1, mii_mode, clock_pads.gtx, ClockSignal("eth_tx")) if isinstance(mii_mode, int) and (mii_mode == 0): - self.comb += self.cd_eth_tx.clk.eq(self.cd_eth_rx.clk) + self.comb += self.cd_eth_tx.clk.eq(self.cd_eth_rx.clk) else: - # XXX Xilinx specific, replace BUFGMUX with a generic clock buffer? - self.specials += Instance("BUFGMUX", - i_I0=self.cd_eth_rx.clk, - i_I1=clock_pads.tx, - i_S=mii_mode, - o_O=self.cd_eth_tx.clk) + # XXX Xilinx specific, replace BUFGMUX with a generic clock buffer? + self.specials += Instance("BUFGMUX", + i_I0=self.cd_eth_rx.clk, + i_I1=clock_pads.tx, + i_S=mii_mode, + o_O=self.cd_eth_tx.clk) reset = Signal() if with_hw_init_reset: diff --git a/setup.py b/setup.py index a0e53b3..413f806 100755 --- a/setup.py +++ b/setup.py @@ -10,26 +10,26 @@ if sys.version_info[:3] < (3, 3): setup( - name="liteeth", - version="0.1", - description="small footprint and configurable Ethernet core", - long_description=open("README").read(), - author="Florent Kermarrec", - author_email="florent@enjoy-digital.fr", - url="http://enjoy-digital.fr", - download_url="https://github.com/enjoy-digital/liteeth", + name="liteeth", + version="0.1", + description="small footprint and configurable Ethernet core", + long_description=open("README").read(), + author="Florent Kermarrec", + author_email="florent@enjoy-digital.fr", + url="http://enjoy-digital.fr", + download_url="https://github.com/enjoy-digital/liteeth", test_suite="test", license="BSD", platforms=["Any"], keywords="HDL ASIC FPGA hardware design", - classifiers=[ - "Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)", - "Environment :: Console", - "Development Status :: Alpha", - "Intended Audience :: Developers", + classifiers=[ + "Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)", + "Environment :: Console", + "Development Status :: Alpha", + "Intended Audience :: Developers", "License :: OSI Approved :: BSD License", - "Operating System :: OS Independent", - "Programming Language :: Python", + "Operating System :: OS Independent", + "Programming Language :: Python", ], packages=find_packages(), include_package_data=True,