Hardware
/
liteeth
mirror of https://github.com/enjoy-digital/liteeth.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #173 from trabucayre/efinix_rework_clkinput_pll 

phy/trionrgmii,titaniumrgmii: replaces str by ClockSignal for ClkInput and PLL
This commit is contained in:
enjoy-digital 2024-09-26 11:51:44 +02:00 committed by GitHub
parent 2b0156e9b3 3696ef82bb
commit 90b1a18485
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
2 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
liteeth/phy/titaniumrgmii.py
View File

@ -131,7 +131,7 @@ class LiteEthPHYRGMIICRG(LiteXModule):
# ------- # -------
self.specials += ClkInput( self.specials += ClkInput(
i = clock_pads.rx, i = clock_pads.rx,
o = f"auto_eth{n}_rx_clk_in", # FIXME: Use Clk Signal. o = self.cd_eth_rx.clk,
) )
# TX Clk. # TX Clk.
@ -144,7 +144,7 @@ class LiteEthPHYRGMIICRG(LiteXModule):
# TX PLL. # TX PLL.
# ------- # -------
self.pll = pll = TITANIUMPLL(platform) self.pll = pll = TITANIUMPLL(platform)
pll.register_clkin(None, freq=125e6, name=f"auto_eth{n}_rx_clk_in0") # FIXME: 0 is to match ClkInput pll.register_clkin(self.cd_eth_rx.clk, freq=125e6)
pll.create_clkout(self.cd_eth_rx, freq=125e6, phase=0, with_reset=False) pll.create_clkout(self.cd_eth_rx, freq=125e6, phase=0, with_reset=False)
pll.create_clkout(self.cd_eth_tx, freq=125e6, phase=0, with_reset=False) pll.create_clkout(self.cd_eth_tx, freq=125e6, phase=0, with_reset=False)
pll.create_clkout(self.cd_eth_tx_delayed, freq=125e6, phase=90) pll.create_clkout(self.cd_eth_tx_delayed, freq=125e6, phase=90)

4
liteeth/phy/trionrgmii.py
View File

@ -131,7 +131,7 @@ class LiteEthPHYRGMIICRG(LiteXModule):
# ------- # -------
self.specials += ClkInput( self.specials += ClkInput(
i = clock_pads.rx, i = clock_pads.rx,
o = f"auto_eth{n}_rx_clk_in", # FIXME: Use Clk Signal. o = self.cd_eth_rx.clk,
) )
# TX Clk. # TX Clk.
@ -144,7 +144,7 @@ class LiteEthPHYRGMIICRG(LiteXModule):
# TX PLL. # TX PLL.
# ------- # -------
self.pll = pll = TRIONPLL(platform) self.pll = pll = TRIONPLL(platform)
pll.register_clkin(None, freq=125e6, name=f"auto_eth{n}_rx_clk_in0") # FIXME: 0 is to match ClkInput pll.register_clkin(self.cd_eth_rx.clk, freq=125e6)
pll.create_clkout(self.cd_eth_rx, freq=125e6, phase=0, with_reset=False, is_feedback=True) pll.create_clkout(self.cd_eth_rx, freq=125e6, phase=0, with_reset=False, is_feedback=True)
pll.create_clkout(self.cd_eth_tx, freq=125e6, phase=0, with_reset=False) pll.create_clkout(self.cd_eth_tx, freq=125e6, phase=0, with_reset=False)
pll.create_clkout(self.cd_eth_tx_delayed, freq=125e6, phase=45) pll.create_clkout(self.cd_eth_tx_delayed, freq=125e6, phase=45)