From 9343889fbd7b9f6edbd661ccfc137885fab13418 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 2 Jul 2021 09:56:55 +0200 Subject: [PATCH] bench: Add KCU105 bench (with KU_1000BASEX on SFP0 and SGMII/RJ45 SFP adapter). --- bench/kcu105.py | 89 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 89 insertions(+) create mode 100755 bench/kcu105.py diff --git a/bench/kcu105.py b/bench/kcu105.py new file mode 100755 index 0000000..236d74b --- /dev/null +++ b/bench/kcu105.py @@ -0,0 +1,89 @@ +#!/usr/bin/env python3 + +# +# This file is part of LiteEth. +# +# Copyright (c) 2021 Florent Kermarrec +# SPDX-License-Identifier: BSD-2-Clause + +import os +import argparse + +from migen import * +from migen.genlib.resetsync import AsyncResetSynchronizer + +from litex_boards.platforms import kcu105 + +from litex.soc.cores.clock import * +from litex.soc.interconnect.csr import * +from litex.soc.integration.soc_core import * +from litex.soc.integration.builder import * + +from liteeth.phy.ku_1000basex import KU_1000BASEX + +# CRG ---------------------------------------------------------------------------------------------- + +class _CRG(Module, AutoCSR): + def __init__(self, platform, sys_clk_freq): + self.clock_domains.cd_sys = ClockDomain() + self.clock_domains.cd_eth = ClockDomain() + + # # # + + # Main PLL. + self.submodules.main_pll = main_pll = USMMCM(speedgrade=-2) + self.comb += main_pll.reset.eq(platform.request("cpu_reset")) + main_pll.register_clkin(platform.request("clk125"), 125e6) + main_pll.create_clkout(self.cd_sys, sys_clk_freq) + main_pll.create_clkout(self.cd_eth, 200e6) + +# Bench SoC ---------------------------------------------------------------------------------------- + +class BenchSoC(SoCCore): + def __init__(self, sys_clk_freq=int(125e6)): + platform = kcu105.Platform() + + # SoCMini ---------------------------------------------------------------------------------- + SoCMini.__init__(self, platform, clk_freq=sys_clk_freq, + ident = "LiteEth bench on KCU105", + ident_version = True + ) + + # CRG -------------------------------------------------------------------------------------- + self.submodules.crg = _CRG(platform, sys_clk_freq) + + # Etherbone -------------------------------------------------------------------------------- + self.submodules.ethphy = KU_1000BASEX(self.crg.cd_eth.clk, + data_pads = self.platform.request("sfp", 0), + sys_clk_freq = self.clk_freq) + self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(1) + self.platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-1753]") + self.add_etherbone(phy=self.ethphy, buffer_depth=255) + + # SRAM ------------------------------------------------------------------------------------- + self.add_ram("sram", 0x20000000, 0x1000) + + # Leds ------------------------------------------------------------------------------------- + from litex.soc.cores.led import LedChaser + self.submodules.leds = LedChaser( + pads = platform.request_all("user_led"), + sys_clk_freq = sys_clk_freq) + +# Main --------------------------------------------------------------------------------------------- + +def main(): + parser = argparse.ArgumentParser(description="LiteEth Bench on KCU105") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + args = parser.parse_args() + + soc = BenchSoC() + builder = Builder(soc, csr_csv="csr.csv") + builder.build(run=args.build) + + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit")) + +if __name__ == "__main__": + main()