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mac/core: Move CSRs to top and rename dw to datapath_dw.

This commit is contained in:
Florent Kermarrec 2021-10-05 13:59:22 +02:00
parent 821f725d58
commit 944849c3cf
1 changed files with 20 additions and 20 deletions
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40
liteeth/mac/core.py
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@ -33,13 +33,19 @@ class LiteEthMACCore(Module, AutoCSR):
raise ValueError("Core data width({}) must be larger than PHY data width({})".format(core_dw, phy.dw)) raise ValueError("Core data width({}) must be larger than PHY data width({})".format(core_dw, phy.dw))
if with_sys_datapath: if with_sys_datapath:
cd_tx = "sys" cd_tx = "sys"
cd_rx = "sys" cd_rx = "sys"
dw = core_dw datapath_dw = core_dw
else: else:
cd_tx = "eth_tx" cd_tx = "eth_tx"
cd_rx = "eth_rx" cd_rx = "eth_rx"
dw = phy.dw datapath_dw = phy.dw
# CSRs.
if with_preamble_crc:
self.preamble_crc = CSRStatus(reset=1)
self.preamble_errors = CSRStatus(32)
self.crc_errors = CSRStatus(32)
# TX Data-Path (Core --> PHY). # TX Data-Path (Core --> PHY).
# ------------------------------------------------------------------------------------------ # ------------------------------------------------------------------------------------------
@ -54,32 +60,28 @@ class LiteEthMACCore(Module, AutoCSR):
# Padding # Padding
if with_padding: if with_padding:
tx_padding = padding.LiteEthMACPaddingInserter(dw, 60) tx_padding = padding.LiteEthMACPaddingInserter(datapath_dw, 60)
tx_padding = ClockDomainsRenamer(cd_tx)(tx_padding) tx_padding = ClockDomainsRenamer(cd_tx)(tx_padding)
self.submodules += tx_padding self.submodules += tx_padding
tx_datapath.append(tx_padding) tx_datapath.append(tx_padding)
# Preamble / CRC # Preamble / CRC
if isinstance(phy, LiteEthPHYModel): if with_preamble_crc:
# In simulation, avoid CRC/Preamble to enable direct connection to the Ethernet tap.
self._preamble_crc = CSRStatus(reset=1)
elif with_preamble_crc:
self._preamble_crc = CSRStatus(reset=1)
# CRC insert. # CRC insert.
tx_crc = crc.LiteEthMACCRC32Inserter(eth_phy_description(dw)) tx_crc = crc.LiteEthMACCRC32Inserter(eth_phy_description(datapath_dw))
tx_crc = BufferizeEndpoints({"sink": DIR_SINK})(tx_crc) # FIXME: Still required? tx_crc = BufferizeEndpoints({"sink": DIR_SINK})(tx_crc) # FIXME: Still required?
tx_crc = ClockDomainsRenamer(cd_tx)(tx_crc) tx_crc = ClockDomainsRenamer(cd_tx)(tx_crc)
self.submodules += tx_crc self.submodules += tx_crc
tx_datapath.append(tx_crc) tx_datapath.append(tx_crc)
# Preamble insert. # Preamble insert.
tx_preamble = preamble.LiteEthMACPreambleInserter(dw) tx_preamble = preamble.LiteEthMACPreambleInserter(datapath_dw)
tx_preamble = ClockDomainsRenamer(cd_tx)(tx_preamble) tx_preamble = ClockDomainsRenamer(cd_tx)(tx_preamble)
self.submodules += tx_preamble self.submodules += tx_preamble
tx_datapath.append(tx_preamble) tx_datapath.append(tx_preamble)
# Interpacket gap # Interpacket gap
tx_gap = gap.LiteEthMACGap(dw) tx_gap = gap.LiteEthMACGap(datapath_dw)
tx_gap = ClockDomainsRenamer(cd_tx)(tx_gap) tx_gap = ClockDomainsRenamer(cd_tx)(tx_gap)
self.submodules += tx_gap self.submodules += tx_gap
tx_datapath.append(tx_gap) tx_datapath.append(tx_gap)
@ -108,14 +110,13 @@ class LiteEthMACCore(Module, AutoCSR):
# Preamble / CRC # Preamble / CRC
if with_preamble_crc: if with_preamble_crc:
# Preamble check. # Preamble check.
rx_preamble = preamble.LiteEthMACPreambleChecker(dw) rx_preamble = preamble.LiteEthMACPreambleChecker(datapath_dw)
rx_preamble = ClockDomainsRenamer(cd_rx)(rx_preamble) rx_preamble = ClockDomainsRenamer(cd_rx)(rx_preamble)
self.submodules += rx_preamble self.submodules += rx_preamble
rx_datapath.append(rx_preamble) rx_datapath.append(rx_preamble)
# Preamble error counter. # Preamble error counter.
self.submodules.ps_preamble_error = PulseSynchronizer(cd_rx, "sys") self.submodules.ps_preamble_error = PulseSynchronizer(cd_rx, "sys")
self.preamble_errors = CSRStatus(32)
self.comb += self.ps_preamble_error.i.eq(rx_preamble.error) self.comb += self.ps_preamble_error.i.eq(rx_preamble.error)
self.sync += [ self.sync += [
If(self.ps_preamble_error.o, If(self.ps_preamble_error.o,
@ -123,14 +124,13 @@ class LiteEthMACCore(Module, AutoCSR):
] ]
# CRC check. # CRC check.
rx_crc = crc.LiteEthMACCRC32Checker(eth_phy_description(dw)) rx_crc = crc.LiteEthMACCRC32Checker(eth_phy_description(datapath_dw))
rx_crc = BufferizeEndpoints({"sink": DIR_SINK})(rx_crc) # FIXME: Still required? rx_crc = BufferizeEndpoints({"sink": DIR_SINK})(rx_crc) # FIXME: Still required?
rx_crc = ClockDomainsRenamer(cd_rx)(rx_crc) rx_crc = ClockDomainsRenamer(cd_rx)(rx_crc)
self.submodules += rx_crc self.submodules += rx_crc
rx_datapath.append(rx_crc) rx_datapath.append(rx_crc)
# CRC error counter. # CRC error counter.
self.crc_errors = CSRStatus(32)
self.submodules.ps_crc_error = PulseSynchronizer(cd_rx, "sys") self.submodules.ps_crc_error = PulseSynchronizer(cd_rx, "sys")
self.comb += self.ps_crc_error.i.eq(rx_crc.error), self.comb += self.ps_crc_error.i.eq(rx_crc.error),
self.sync += [ self.sync += [
@ -141,7 +141,7 @@ class LiteEthMACCore(Module, AutoCSR):
# Padding. # Padding.
if with_padding: if with_padding:
rx_padding = padding.LiteEthMACPaddingChecker(dw, 60) rx_padding = padding.LiteEthMACPaddingChecker(datapath_dw, 60)
rx_padding = ClockDomainsRenamer(cd_rx)(rx_padding) rx_padding = ClockDomainsRenamer(cd_rx)(rx_padding)
self.submodules += rx_padding self.submodules += rx_padding
rx_datapath.append(rx_padding) rx_datapath.append(rx_padding)