From 94af3d63d9a8489b6789a1471550021326333372 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 31 Aug 2018 08:26:37 +0200 Subject: [PATCH] README: update and rename example_designs to examples --- README | 26 +++++-------------- {example_designs => examples}/__init__.py | 0 {example_designs => examples}/make.py | 0 .../targets/Makefile | 0 .../targets/__init__.py | 0 {example_designs => examples}/targets/base.py | 0 {example_designs => examples}/targets/core.py | 0 .../targets/etherbone.py | 0 {example_designs => examples}/targets/tty.py | 0 {example_designs => examples}/targets/udp.py | 0 .../test/test_analyzer.py | 0 .../test/test_etherbone.py | 0 .../test/test_regs.py | 0 .../test/test_tty.py | 0 .../test/test_udp.py | 0 setup.py | 2 +- test/Makefile | 20 +++++++------- 17 files changed, 18 insertions(+), 30 deletions(-) rename {example_designs => examples}/__init__.py (100%) rename {example_designs => examples}/make.py (100%) rename {example_designs => examples}/targets/Makefile (100%) rename {example_designs => examples}/targets/__init__.py (100%) rename {example_designs => examples}/targets/base.py (100%) rename {example_designs => examples}/targets/core.py (100%) rename {example_designs => examples}/targets/etherbone.py (100%) rename {example_designs => examples}/targets/tty.py (100%) rename {example_designs => examples}/targets/udp.py (100%) rename {example_designs => examples}/test/test_analyzer.py (100%) rename {example_designs => examples}/test/test_etherbone.py (100%) rename {example_designs => examples}/test/test_regs.py (100%) rename {example_designs => examples}/test/test_tty.py (100%) rename {example_designs => examples}/test/test_udp.py (100%) diff --git a/README b/README index cacb88c..b1fa7d6 100644 --- a/README +++ b/README @@ -16,13 +16,7 @@ LiteEth is part of LiteX libraries whose aims are to lower entry level of complex FPGA cores by providing simple, elegant and efficient implementations of components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller... -Since Python is used to describe the HDL, the core is highly and easily -configurable. - -LiteEth is built using LiteX and uses technologies developed in partnership with -M-Labs Ltd: - - Migen enables generating HDL with Python in an efficient way. - - MiSoC provides the basic blocks to build a powerful and small footprint SoC. +Using Migen to describe the HDL allows the core to be highly and easily configurable. LiteEth can be used as LiteX library or can be integrated with your standard design flow by generating the verilog rtl that you will use as a standard core. @@ -30,18 +24,13 @@ design flow by generating the verilog rtl that you will use as a standard core. [> Features ----------- PHY: - - MII / RMII - - GMII / RGMII - - 1000BaseX + - MII, RMII 100Mbps PHYs. + - GMII / RGMII /1000BaseX 1Gbps PHYs. Core: - - MAC with various interfaces (to soft core or hardware stack) - - ARP - - ICMP - - UDP + - Configurable MAC (HW or SW interface) + - ARP / ICMP / UDP (HW or SW) Frontend: - - Etherbone (Wishbone over UDP, Slave or Master support) - - Virtual Serial ports over UDP. - + - Etherbone (Wishbone over UDP: Slave or Master support) [> FPGA Proven --------------- @@ -53,7 +42,6 @@ LiteEth is already used in commercial and open-source designs: [> Possible improvements ------------------------ -- optimize ressources on HW ICMP and Etherbone (parameters buffering) - add standardized interfaces (AXI, Avalon-ST) - add DMA interface to MAC - add more documentation @@ -73,7 +61,7 @@ enjoy-digital.fr. python3 setup.py develop cd .. -3. TODO: add/describe example design(s) +3. TODO: add/describe examples [> Tests -------- diff --git a/example_designs/__init__.py b/examples/__init__.py similarity index 100% rename from example_designs/__init__.py rename to examples/__init__.py diff --git a/example_designs/make.py b/examples/make.py similarity index 100% rename from example_designs/make.py rename to examples/make.py diff --git a/example_designs/targets/Makefile b/examples/targets/Makefile similarity index 100% rename from example_designs/targets/Makefile rename to examples/targets/Makefile diff --git a/example_designs/targets/__init__.py b/examples/targets/__init__.py similarity index 100% rename from example_designs/targets/__init__.py rename to examples/targets/__init__.py diff --git a/example_designs/targets/base.py b/examples/targets/base.py similarity index 100% rename from example_designs/targets/base.py rename to examples/targets/base.py diff --git a/example_designs/targets/core.py b/examples/targets/core.py similarity index 100% rename from example_designs/targets/core.py rename to examples/targets/core.py diff --git a/example_designs/targets/etherbone.py b/examples/targets/etherbone.py similarity index 100% rename from example_designs/targets/etherbone.py rename to examples/targets/etherbone.py diff --git a/example_designs/targets/tty.py b/examples/targets/tty.py similarity index 100% rename from example_designs/targets/tty.py rename to examples/targets/tty.py diff --git a/example_designs/targets/udp.py b/examples/targets/udp.py similarity index 100% rename from example_designs/targets/udp.py rename to examples/targets/udp.py diff --git a/example_designs/test/test_analyzer.py b/examples/test/test_analyzer.py similarity index 100% rename from example_designs/test/test_analyzer.py rename to examples/test/test_analyzer.py diff --git a/example_designs/test/test_etherbone.py b/examples/test/test_etherbone.py similarity index 100% rename from example_designs/test/test_etherbone.py rename to examples/test/test_etherbone.py diff --git a/example_designs/test/test_regs.py b/examples/test/test_regs.py similarity index 100% rename from example_designs/test/test_regs.py rename to examples/test/test_regs.py diff --git a/example_designs/test/test_tty.py b/examples/test/test_tty.py similarity index 100% rename from example_designs/test/test_tty.py rename to examples/test/test_tty.py diff --git a/example_designs/test/test_udp.py b/examples/test/test_udp.py similarity index 100% rename from example_designs/test/test_udp.py rename to examples/test/test_udp.py diff --git a/setup.py b/setup.py index 45dddf2..6cdc359 100755 --- a/setup.py +++ b/setup.py @@ -31,6 +31,6 @@ setup( "Operating System :: OS Independent", "Programming Language :: Python", ], - packages=find_packages(exclude=("test*", "sim*", "doc*", "example_designs*")), + packages=find_packages(exclude=("test*", "sim*", "doc*", "examples*")), include_package_data=True, ) diff --git a/test/Makefile b/test/Makefile index 36575a1..20cdf25 100644 --- a/test/Makefile +++ b/test/Makefile @@ -10,14 +10,14 @@ model_tb: cd ../ && PYTHONPATH=./ $(CMD) test/model/icmp.py cd ../ && PYTHONPATH=./ $(CMD) test/model/etherbone.py -example_designs: - cd ../example_designs && $(PYTHON) make.py -t base -s BaseSoC -p kc705 -Ob run False build-bitstream - cd ../example_designs && $(PYTHON) make.py -t base -s BaseSoCDevel -p kc705 -Ob run False build-bitstream - cd ../example_designs && $(PYTHON) make.py -t udp -s UDPSoC -p kc705 -Ob run False build-bitstream - cd ../example_designs && $(PYTHON) make.py -t udp -s UDPSoCDevel -p kc705 -Ob run False build-bitstream - cd ../example_designs && $(PYTHON) make.py -t etherbone -s EtherboneSoC -p kc705 -Ob run False build-bitstream - cd ../example_designs && $(PYTHON) make.py -t etherbone -s EtherboneSoCDevel -p kc705 -Ob run False build-bitstream - cd ../example_designs && $(PYTHON) make.py -t tty -s TTYSoC -p kc705 -Ob run False build-bitstream - cd ../example_designs && $(PYTHON) make.py -t tty -s TTYSoCDevel -p kc705 -Ob run False build-bitstream +examples: + cd ../examples && $(PYTHON) make.py -t base -s BaseSoC -p kc705 -Ob run False build-bitstream + cd ../examples && $(PYTHON) make.py -t base -s BaseSoCDevel -p kc705 -Ob run False build-bitstream + cd ../examples && $(PYTHON) make.py -t udp -s UDPSoC -p kc705 -Ob run False build-bitstream + cd ../examples && $(PYTHON) make.py -t udp -s UDPSoCDevel -p kc705 -Ob run False build-bitstream + cd ../examples && $(PYTHON) make.py -t etherbone -s EtherboneSoC -p kc705 -Ob run False build-bitstream + cd ../examples && $(PYTHON) make.py -t etherbone -s EtherboneSoCDevel -p kc705 -Ob run False build-bitstream + cd ../examples && $(PYTHON) make.py -t tty -s TTYSoC -p kc705 -Ob run False build-bitstream + cd ../examples && $(PYTHON) make.py -t tty -s TTYSoCDevel -p kc705 -Ob run False build-bitstream -all: model_tb example_designs \ No newline at end of file +all: model_tb examples \ No newline at end of file