README: update and rename example_designs to examples

README

@@ -16,13 +16,7 @@ LiteEth is part of LiteX libraries whose aims are to lower entry level of
 complex FPGA cores by providing simple, elegant and efficient implementations
 of components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
 
-Since Python is used to describe the HDL, the core is highly and easily
+Using Migen to describe the HDL allows the core to be highly and easily configurable.
-configurable.
-
-LiteEth is built using LiteX and uses technologies developed in partnership with
-M-Labs Ltd:
- - Migen enables generating HDL with Python in an efficient way.
- - MiSoC provides the basic blocks to build a powerful and small footprint SoC.
 
 LiteEth can be used as LiteX library or can be integrated with your standard
 design flow by generating the verilog rtl that you will use as a standard core.
@@ -30,18 +24,13 @@ design flow by generating the verilog rtl that you will use as a standard core.
 [> Features
 -----------
 PHY:
-  - MII / RMII
+  - MII, RMII 100Mbps PHYs.
-  - GMII / RGMII
+  - GMII / RGMII /1000BaseX 1Gbps PHYs.
-  - 1000BaseX
 Core:
-  - MAC with various interfaces (to soft core or hardware stack)
+  - Configurable MAC (HW or SW interface)
-  - ARP
+  - ARP / ICMP / UDP (HW or SW)
-  - ICMP
-  - UDP
 Frontend:
-  - Etherbone (Wishbone over UDP, Slave or Master support)
+  - Etherbone (Wishbone over UDP: Slave or Master support)
-  - Virtual Serial ports over UDP.
-
 
 [> FPGA Proven
 ---------------
@@ -53,7 +42,6 @@ LiteEth is already used in commercial and open-source designs:
 
 [> Possible improvements
 ------------------------
-- optimize ressources on HW ICMP and Etherbone (parameters buffering)
 - add standardized interfaces (AXI, Avalon-ST)
 - add DMA interface to MAC
 - add more documentation
@@ -73,7 +61,7 @@ enjoy-digital.fr.
   python3 setup.py develop
   cd ..
 
-3. TODO: add/describe example design(s)
+3. TODO: add/describe examples
 
 [> Tests
 --------

setup.py

@@ -31,6 +31,6 @@ setup(
         "Operating System :: OS Independent",
         "Programming Language :: Python",
     ],
-    packages=find_packages(exclude=("test*", "sim*", "doc*", "example_designs*")),
+    packages=find_packages(exclude=("test*", "sim*", "doc*", "examples*")),
     include_package_data=True,
 )

test/Makefile

@@ -10,14 +10,14 @@ model_tb:
 	cd ../ && PYTHONPATH=./ $(CMD) test/model/icmp.py
 	cd ../ && PYTHONPATH=./ $(CMD) test/model/etherbone.py
 
-example_designs:
+examples:
-	cd ../example_designs && $(PYTHON) make.py -t base -s BaseSoC -p kc705 -Ob run False build-bitstream
+	cd ../examples && $(PYTHON) make.py -t base -s BaseSoC -p kc705 -Ob run False build-bitstream
-	cd ../example_designs && $(PYTHON) make.py -t base -s BaseSoCDevel -p kc705 -Ob run False build-bitstream
+	cd ../examples && $(PYTHON) make.py -t base -s BaseSoCDevel -p kc705 -Ob run False build-bitstream
-	cd ../example_designs && $(PYTHON) make.py -t udp -s UDPSoC -p kc705 -Ob run False build-bitstream
+	cd ../examples && $(PYTHON) make.py -t udp -s UDPSoC -p kc705 -Ob run False build-bitstream
-	cd ../example_designs && $(PYTHON) make.py -t udp -s UDPSoCDevel -p kc705 -Ob run False build-bitstream
+	cd ../examples && $(PYTHON) make.py -t udp -s UDPSoCDevel -p kc705 -Ob run False build-bitstream
-	cd ../example_designs && $(PYTHON) make.py -t etherbone -s EtherboneSoC -p kc705 -Ob run False build-bitstream
+	cd ../examples && $(PYTHON) make.py -t etherbone -s EtherboneSoC -p kc705 -Ob run False build-bitstream
-	cd ../example_designs && $(PYTHON) make.py -t etherbone -s EtherboneSoCDevel -p kc705 -Ob run False build-bitstream
+	cd ../examples && $(PYTHON) make.py -t etherbone -s EtherboneSoCDevel -p kc705 -Ob run False build-bitstream
-	cd ../example_designs && $(PYTHON) make.py -t tty -s TTYSoC -p kc705 -Ob run False build-bitstream
+	cd ../examples && $(PYTHON) make.py -t tty -s TTYSoC -p kc705 -Ob run False build-bitstream
-	cd ../example_designs && $(PYTHON) make.py -t tty -s TTYSoCDevel -p kc705 -Ob run False build-bitstream
+	cd ../examples && $(PYTHON) make.py -t tty -s TTYSoCDevel -p kc705 -Ob run False build-bitstream
 
-all: model_tb example_designs
+all: model_tb examples