diff --git a/examples/udp_a7_gtp_sgmii.yml b/examples/udp_a7_gtp_sgmii.yml
index 6e04423..f7cf9da 100644
--- a/examples/udp_a7_gtp_sgmii.yml
+++ b/examples/udp_a7_gtp_sgmii.yml
@@ -10,7 +10,7 @@ vendor    : xilinx
 toolchain : vivado
 
 # Core ---------------------------------------------------------------------
-refclk_freq : 200e6
+refclk_freq : 156.25e6
 clk_freq    : 25e6
 core        : udp
 data_width  : 32
diff --git a/liteeth/gen.py b/liteeth/gen.py
index 43a05c2..b63117e 100755
--- a/liteeth/gen.py
+++ b/liteeth/gen.py
@@ -286,12 +286,12 @@ class PHYCore(SoCMini):
             ethphy_pads = platform.request("sgmii")
             # Artix7.
             if phy in [liteeth_phys.A7_1000BASEX]:
-                assert core_config.get("refclk_freq", 0) == 200e6
+                assert core_config.get("refclk_freq", 0) in [125e6, 156.25e6]
                 from liteeth.phy.a7_gtp import QPLLSettings, QPLL
                 qpll_settings = QPLLSettings(
                     refclksel  = 0b001,
                     fbdiv      = 4,
-                    fbdiv_45   = 5,
+                    fbdiv_45   = {125e6:5, 156.25e6:4},
                     refclk_div = 1
                 )
                 qpll = QPLL(ethphy_pads.refclk, qpll_settings)