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liteeth_gen/A7_1000BASEX: Add support for 156.25MHz refclk_freq and fix 200MHz to 125MHz.

This commit is contained in:
Florent Kermarrec 2024-01-19 21:40:45 +01:00
parent c05de191e2
commit 95081445e7
2 changed files with 3 additions and 3 deletions
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2
examples/udp_a7_gtp_sgmii.yml
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@ -10,7 +10,7 @@ vendor : xilinx
toolchain : vivado
# Core ---------------------------------------------------------------------
refclk_freq : 200e6
refclk_freq : 156.25e6
clk_freq : 25e6
core : udp
data_width : 32

4
liteeth/gen.py
View File

@ -286,12 +286,12 @@ class PHYCore(SoCMini):
ethphy_pads = platform.request("sgmii")
# Artix7.
if phy in [liteeth_phys.A7_1000BASEX]:
assert core_config.get("refclk_freq", 0) == 200e6
assert core_config.get("refclk_freq", 0) in [125e6, 156.25e6]
from liteeth.phy.a7_gtp import QPLLSettings, QPLL
qpll_settings = QPLLSettings(
refclksel = 0b001,
fbdiv = 4,
fbdiv_45 = 5,
fbdiv_45 = {125e6:5, 156.25e6:4},
refclk_div = 1
)
qpll = QPLL(ethphy_pads.refclk, qpll_settings)