From 9593e297567073e8dbf58758914858e057e33acf Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 15 Mar 2016 15:40:06 +0100 Subject: [PATCH] global: use 192.168.1.100 (remote)/ 192.168.1.50 (local) IP addresses --- README | 4 ++-- example_designs/targets/base.py | 2 +- example_designs/targets/core.py | 6 +++--- example_designs/targets/etherbone.py | 2 +- example_designs/targets/tty.py | 4 ++-- example_designs/targets/udp.py | 2 +- example_designs/test/test_etherbone.py | 6 +++--- example_designs/test/test_tty.py | 2 +- example_designs/test/test_udp.py | 4 ++-- liteeth/phy/model.py | 2 +- 10 files changed, 17 insertions(+), 17 deletions(-) diff --git a/README b/README index 806de0e..d009580 100644 --- a/README +++ b/README @@ -74,7 +74,7 @@ devel [AT] lists.m-labs.hk. run ./make.py -t udp all load-bitstream 4. Test design (only for KC705 for now): - try to ping 192.168.0.42 + try to ping 192.168.1.50 go to example_designs/test/ run ./test_udp.py @@ -82,7 +82,7 @@ devel [AT] lists.m-labs.hk. python3 make.py -t etherbone all load-bitstream 6. Test design (only for KC705 for now): - try to ping 192.168.0.42 + try to ping 192.168.1.50 go to example_designs/test/ run ./test_etherbone.py diff --git a/example_designs/targets/base.py b/example_designs/targets/base.py index d7e168c..c591fe8 100644 --- a/example_designs/targets/base.py +++ b/example_designs/targets/base.py @@ -20,7 +20,7 @@ class BaseSoC(SoCCore): csr_map.update(SoCCore.csr_map) def __init__(self, platform, clk_freq=166*1000000, mac_address=0x10e2d5000000, - ip_address="192.168.0.42"): + ip_address="192.168.1.50"): clk_freq = int((1/(platform.default_clk_period))*1000000000) SoCCore.__init__(self, platform, clk_freq, cpu_type=None, diff --git a/example_designs/targets/core.py b/example_designs/targets/core.py index 6434f13..a8b89e5 100644 --- a/example_designs/targets/core.py +++ b/example_designs/targets/core.py @@ -138,7 +138,7 @@ _io = [ # payload Subsignal("data", Pins(32)), Subsignal("error", Pins(4)) - ), + ), ] class CorePlatform(XilinxPlatform): @@ -197,7 +197,7 @@ class MACCore(PHYCore): "ethmac": 0x50000000 } mem_map.update(SoCCore.mem_map) - + def __init__(self, phy, clk_freq): PHYCore.__init__(self, phy, clk_freq) @@ -265,7 +265,7 @@ def main(): parser.add_argument("--phy", default="MII", help="Ethernet PHY(MII/RMII/GMII/RMGII)") parser.add_argument("--core", default="wishbone", help="Ethernet Core(wishbone/udp)") parser.add_argument("--mac_address", default=0x10e2d5000000, help="MAC address") - parser.add_argument("--ip_address", default="192.168.0.42", help="IP address") + parser.add_argument("--ip_address", default="192.168.1.50", help="IP address") args = parser.parse_args() if args.core == "mac": diff --git a/example_designs/targets/etherbone.py b/example_designs/targets/etherbone.py index 73fbc6d..7df6990 100644 --- a/example_designs/targets/etherbone.py +++ b/example_designs/targets/etherbone.py @@ -9,7 +9,7 @@ class EtherboneSoC(BaseSoC): def __init__(self, platform): BaseSoC.__init__(self, platform, mac_address=0x10e2d5000000, - ip_address="192.168.0.42") + ip_address="192.168.1.50") self.submodules.etherbone = LiteEthEtherbone(self.core.udp, 20000) self.add_wb_master(self.etherbone.master.bus) diff --git a/example_designs/targets/tty.py b/example_designs/targets/tty.py index 32dce9a..1343a31 100644 --- a/example_designs/targets/tty.py +++ b/example_designs/targets/tty.py @@ -9,8 +9,8 @@ class TTYSoC(BaseSoC): def __init__(self, platform): BaseSoC.__init__(self, platform, mac_address=0x10e2d5000000, - ip_address="192.168.0.42") - self.submodules.tty = LiteEthTTY(self.core.udp, convert_ip("192.168.0.14"), 10000) + ip_address="192.168.1.50") + self.submodules.tty = LiteEthTTY(self.core.udp, convert_ip("192.168.1.100"), 10000) self.comb += self.tty.source.connect(self.tty.sink) diff --git a/example_designs/targets/udp.py b/example_designs/targets/udp.py index d85c2d3..c64b7fb 100644 --- a/example_designs/targets/udp.py +++ b/example_designs/targets/udp.py @@ -10,7 +10,7 @@ class UDPSoC(BaseSoC): def __init__(self, platform): BaseSoC.__init__(self, platform, mac_address=0x10e2d5000000, - ip_address="192.168.0.42") + ip_address="192.168.1.50") # add udp loopback on port 6000 with dw=8 self.add_udp_loopback(6000, 8, 8192, "loopback_8") diff --git a/example_designs/test/test_etherbone.py b/example_designs/test/test_etherbone.py index e7d2bc5..5f737ea 100644 --- a/example_designs/test/test_etherbone.py +++ b/example_designs/test/test_etherbone.py @@ -10,7 +10,7 @@ socket = socket.socket(socket.AF_INET, socket.SOCK_DGRAM) packet = EtherbonePacket() packet.pf = 1 packet.encode() -socket.sendto(bytes(packet), ("192.168.0.42", 20000)) +socket.sendto(bytes(packet), ("192.168.1.50", 20000)) time.sleep(0.01) # test writes @@ -23,7 +23,7 @@ record.wcount = len(writes_datas) packet = EtherbonePacket() packet.records = [record] packet.encode() -socket.sendto(bytes(packet), ("192.168.0.42", 20000)) +socket.sendto(bytes(packet), ("192.168.1.50", 20000)) time.sleep(0.01) # test reads @@ -36,5 +36,5 @@ record.rcount = len(reads_addrs) packet = EtherbonePacket() packet.records = [record] packet.encode() -socket.sendto(bytes(packet), ("192.168.0.42", 20000)) +socket.sendto(bytes(packet), ("192.168.1.50", 20000)) time.sleep(0.01) diff --git a/example_designs/test/test_tty.py b/example_designs/test/test_tty.py index 759e589..fb66012 100644 --- a/example_designs/test/test_tty.py +++ b/example_designs/test/test_tty.py @@ -36,6 +36,6 @@ def test(fpga_ip, udp_port, test_message): # # # test_message = "LiteEth virtual TTY Hello world\n" -test("192.168.0.42", 10000, test_message) +test("192.168.1.50", 10000, test_message) # # # \ No newline at end of file diff --git a/example_designs/test/test_udp.py b/example_designs/test/test_udp.py index 9f8d13b..62c27d9 100644 --- a/example_designs/test/test_udp.py +++ b/example_designs/test/test_udp.py @@ -82,7 +82,7 @@ def test(fpga_ip, udp_port, test_size): # # # -test("192.168.0.42", 6000, 128*KB) -test("192.168.0.42", 8000, 128*KB) +test("192.168.1.50", 6000, 128*KB) +test("192.168.1.50", 8000, 128*KB) # # # \ No newline at end of file diff --git a/liteeth/phy/model.py b/liteeth/phy/model.py index 1633c73..05f4cc1 100644 --- a/liteeth/phy/model.py +++ b/liteeth/phy/model.py @@ -24,7 +24,7 @@ class LiteEthPHYModelCRG(Module, AutoCSR): class LiteEthPHYModel(Module, AutoCSR): - def __init__(self, pads, tap="tap0", ip_address="192.168.0.14"): + def __init__(self, pads, tap="tap0", ip_address="192.168.1.100"): self.dw = 8 self.submodules.crg = LiteEthPHYModelCRG() self.sink = sink = Sink(eth_phy_description(8))