From 9635a947695862529865b06cb926f04752c871fe Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sat, 24 Oct 2015 14:00:33 +0200 Subject: [PATCH] README: cleanup --- README | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/README b/README index bfcfa98..2834991 100644 --- a/README +++ b/README @@ -43,7 +43,7 @@ design flow by generating the verilog rtl that you will use as a standard core. [> Proven ---------- -LiteEth is already used by commercial and open-source designs: +LiteEth is already used in commercial and open-source designs: - MiSoC: http://m-labs.hk/gateware.html - ARTIQ: http://m-labs.hk/artiq/index.html - HDMI2USB: http://hdmi2usb.tv/home/ @@ -77,12 +77,12 @@ devel [AT] lists.m-labs.hk. git clone https://github.com/m-labs/misoc --recursive 4. Build and load UDP loopback design (only for KC705 for now): - go to ./example_designs/ + go to example_designs/ run ./make.py -t udp all load-bitstream 5. Test design (only for KC705 for now): try to ping 192.168.0.42 - go to [..]/example_designs/test/ + go to example_designs/test/ run ./make.py test_udp 6. Build and load Etherbone design (only for KC705 for now): @@ -90,12 +90,12 @@ devel [AT] lists.m-labs.hk. 7. Test design (only for KC705 for now): try to ping 192.168.0.42 - go to [..]/example_designs/test/ + go to example_designs/test/ run ./make.py test_etherbone [> Simulations --------------- - Simulations are available in ./test/: + Simulations are available in test/: - mac_core_tb - mac_wishbone_tb - arp_tb @@ -104,7 +104,7 @@ devel [AT] lists.m-labs.hk. - udp_tb All ethernet layers have their own model tested against real ethernet dumps (dumps.py) To run a simulation: - go to ./test/ + go to test/ make [> Tests