From 2b6d4ee51b0dff67bc0cb99f70171549d7f3506f Mon Sep 17 00:00:00 2001 From: Arne Jansen Date: Thu, 8 Dec 2022 09:58:01 +0100 Subject: [PATCH 1/2] wishbone: fix race condition in rx path When no rx slot is available, the current code path sends the FSM through DISCARD-REMAINING to TERMINATE, which tries to signal the slot to the user even though nothing has been received. This can lead to data corruption. --- liteeth/mac/sram.py | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/liteeth/mac/sram.py b/liteeth/mac/sram.py index 06f0bcf..295c6fe 100644 --- a/liteeth/mac/sram.py +++ b/liteeth/mac/sram.py @@ -91,7 +91,7 @@ class LiteEthMACSRAMWriter(Module, AutoCSR): ) ).Else( NextValue(errors, errors + 1), - NextState("DISCARD-REMAINING") + NextState("DISCARD-ALL") ) ) ) @@ -104,6 +104,16 @@ class LiteEthMACSRAMWriter(Module, AutoCSR): ) ) ) + fsm.act("DISCARD-ALL", + If(sink.valid & sink.last, + If((sink.last_be) != 0, + NextState("DISCARD") + ).Else( + NextValue(length, 0), + NextState("WRITE") + ) + ) + ) fsm.act("DISCARD", NextValue(length, 0), NextState("WRITE") From 004e3f59d77bccc1b4ba33b1f32eb13a4e68015e Mon Sep 17 00:00:00 2001 From: Arne Jansen Date: Thu, 8 Dec 2022 18:11:01 +0100 Subject: [PATCH 2/2] mac: fix typo --- liteeth/mac/wishbone.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/liteeth/mac/wishbone.py b/liteeth/mac/wishbone.py index 9a76dfc..f32b346 100644 --- a/liteeth/mac/wishbone.py +++ b/liteeth/mac/wishbone.py @@ -40,7 +40,7 @@ class LiteEthMACWishboneInterface(Module, AutoCSR): # Wishbone SRAM interfaces for the reader SRAM (i.e. Ethernet TX). wb_tx_sram_ifs = [] - for n in range(nrxslots): + for n in range(ntxslots): wb_tx_sram_ifs.append(wishbone.SRAM( mem_or_size = self.sram.reader.mems[n], read_only = False,