Hardware
/
liteeth
mirror of https://github.com/enjoy-digital/liteeth.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #124 from sensille/wishbone_rx 

wishbone rx data corruption
This commit is contained in:
enjoy-digital 2022-12-20 09:53:34 +01:00 committed by GitHub
parent 0e1a1da036 004e3f59d7
commit 97dccdb294
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 12 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
liteeth/mac/sram.py
View File

@ -91,7 +91,7 @@ class LiteEthMACSRAMWriter(Module, AutoCSR):
) )
).Else( ).Else(
NextValue(errors, errors + 1), NextValue(errors, errors + 1),
NextState("DISCARD-REMAINING") NextState("DISCARD-ALL")
) )
) )
) )
@ -104,6 +104,16 @@ class LiteEthMACSRAMWriter(Module, AutoCSR):
) )
) )
) )
fsm.act("DISCARD-ALL",
If(sink.valid & sink.last,
If((sink.last_be) != 0,
NextState("DISCARD")
).Else(
NextValue(length, 0),
NextState("WRITE")
)
)
)
fsm.act("DISCARD", fsm.act("DISCARD",
NextValue(length, 0), NextValue(length, 0),
NextState("WRITE") NextState("WRITE")

2
liteeth/mac/wishbone.py
View File

@ -40,7 +40,7 @@ class LiteEthMACWishboneInterface(Module, AutoCSR):
# Wishbone SRAM interfaces for the reader SRAM (i.e. Ethernet TX). # Wishbone SRAM interfaces for the reader SRAM (i.e. Ethernet TX).
wb_tx_sram_ifs = [] wb_tx_sram_ifs = []
for n in range(nrxslots): for n in range(ntxslots):
wb_tx_sram_ifs.append(wishbone.SRAM( wb_tx_sram_ifs.append(wishbone.SRAM(
mem_or_size = self.sram.reader.mems[n], mem_or_size = self.sram.reader.mems[n],
read_only = False, read_only = False,