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phy/rgmii: cleanup primitive instances

This commit is contained in:
Florent Kermarrec 2020-01-28 10:41:32 +01:00
parent 8a4f38339a
commit 983017a9ed
4 changed files with 371 additions and 280 deletions
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119
liteeth/phy/ecp5rgmii.py
View File

@ -21,38 +21,39 @@ class LiteEthPHYRGMIITX(Module):
self.specials += [
Instance("ODDRX1F",
i_SCLK=ClockSignal("eth_tx"),
i_RST=ResetSignal("eth_tx"),
i_D0=sink.valid,
i_D1=sink.valid,
o_Q=tx_ctl_oddrx1f
i_SCLK = ClockSignal("eth_tx"),
i_RST = ResetSignal("eth_tx"),
i_D0 = sink.valid,
i_D1 = sink.valid,
o_Q = tx_ctl_oddrx1f
),
Instance("DELAYF",
p_DEL_MODE="SCLK_ALIGNED",
p_DEL_VALUE="DELAY0",
i_LOADN=1,
i_MOVE=0,
i_DIRECTION=0,
i_A=tx_ctl_oddrx1f,
o_Z=pads.tx_ctl)
p_DEL_MODE = "SCLK_ALIGNED",
p_DEL_VALUE = "DELAY0",
i_LOADN = 1,
i_MOVE = 0,
i_DIRECTION = 0,
i_A = tx_ctl_oddrx1f,
o_Z = pads.tx_ctl)
]
for i in range(4):
self.specials += [
Instance("ODDRX1F",
i_SCLK=ClockSignal("eth_tx"),
i_RST=ResetSignal("eth_tx"),
i_D0=sink.data[i],
i_D1=sink.data[4+i],
o_Q=tx_data_oddrx1f[i]
i_SCLK = ClockSignal("eth_tx"),
i_RST = ResetSignal("eth_tx"),
i_D0 = sink.data[i],
i_D1 = sink.data[4+i],
o_Q = tx_data_oddrx1f[i]
),
Instance("DELAYF",
p_DEL_MODE="SCLK_ALIGNED",
p_DEL_VALUE="DELAY0",
i_LOADN=1,
i_MOVE=0,
i_DIRECTION=0,
i_A=tx_data_oddrx1f[i],
o_Z=pads.tx_data[i])
p_DEL_MODE = "SCLK_ALIGNED",
p_DEL_VALUE = "DELAY0",
i_LOADN = 1,
i_MOVE = 0,
i_DIRECTION = 0,
i_A = tx_data_oddrx1f[i],
o_Z = pads.tx_data[i]
)
]
self.comb += sink.ready.eq(1)
@ -75,37 +76,37 @@ class LiteEthPHYRGMIIRX(Module):
self.specials += [
Instance("DELAYF",
p_DEL_MODE="SCLK_ALIGNED",
p_DEL_VALUE="DELAY{}".format(rx_delay_taps),
i_LOADN=1,
i_MOVE=0,
i_DIRECTION=0,
i_A=pads.rx_ctl,
o_Z=rx_ctl_delayf),
p_DEL_MODE = "SCLK_ALIGNED",
p_DEL_VALUE = "DELAY{}".format(rx_delay_taps),
i_LOADN = 1,
i_MOVE = 0,
i_DIRECTION = 0,
i_A = pads.rx_ctl,
o_Z = rx_ctl_delayf),
Instance("IDDRX1F",
i_SCLK=ClockSignal("eth_rx"),
i_RST=ResetSignal("eth_rx"),
i_D=rx_ctl_delayf,
o_Q0=rx_ctl,
i_SCLK = ClockSignal("eth_rx"),
i_RST = ResetSignal("eth_rx"),
i_D = rx_ctl_delayf,
o_Q0 = rx_ctl,
)
]
self.sync += rx_ctl_reg.eq(rx_ctl)
for i in range(4):
self.specials += [
Instance("DELAYF",
p_DEL_MODE="SCLK_ALIGNED",
p_DEL_VALUE="DELAY{}".format(rx_delay_taps),
i_LOADN=1,
i_MOVE=0,
i_DIRECTION=0,
i_A=pads.rx_data[i],
o_Z=rx_data_delayf[i]),
p_DEL_MODE = "SCLK_ALIGNED",
p_DEL_VALUE = "DELAY{}".format(rx_delay_taps),
i_LOADN = 1,
i_MOVE = 0,
i_DIRECTION = 0,
i_A = pads.rx_data[i],
o_Z = rx_data_delayf[i]),
Instance("IDDRX1F",
i_SCLK=ClockSignal("eth_rx"),
i_RST=ResetSignal("eth_rx"),
i_D=rx_data_delayf[i],
o_Q0=rx_data[i],
o_Q1=rx_data[i+4]
i_SCLK = ClockSignal("eth_rx"),
i_RST = ResetSignal("eth_rx"),
i_D = rx_data_delayf[i],
o_Q0 = rx_data[i],
o_Q1 = rx_data[i+4]
)
]
self.sync += rx_data_reg.eq(rx_data)
@ -143,20 +144,20 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR):
eth_tx_clk_o = Signal()
self.specials += [
Instance("ODDRX1F",
i_SCLK=ClockSignal("eth_tx"),
i_RST=ResetSignal("eth_tx"),
i_D0=1,
i_D1=0,
o_Q=eth_tx_clk_o
i_SCLK = ClockSignal("eth_tx"),
i_RST = ResetSignal("eth_tx"),
i_D0 = 1,
i_D1 = 0,
o_Q = eth_tx_clk_o
),
Instance("DELAYF",
p_DEL_MODE="SCLK_ALIGNED",
p_DEL_VALUE="DELAY{}".format(tx_delay_taps),
i_LOADN=1,
i_MOVE=0,
i_DIRECTION=0,
i_A=eth_tx_clk_o,
o_Z=clock_pads.tx)
p_DEL_MODE = "SCLK_ALIGNED",
p_DEL_VALUE = "DELAY{}".format(tx_delay_taps),
i_LOADN = 1,
i_MOVE = 0,
i_DIRECTION = 0,
i_A = eth_tx_clk_o,
o_Z = clock_pads.tx)
]
# Reset

254
liteeth/phy/s6rgmii.py
View File

@ -21,63 +21,63 @@ class LiteEthPHYRGMIITX(Module):
self.specials += [
Instance("ODDR2",
p_DDR_ALIGNMENT="C0",
p_SRTYPE="ASYNC",
o_Q=tx_ctl_obuf,
i_C0=ClockSignal("eth_tx"),
i_C1=~ClockSignal("eth_tx"),
i_CE=1,
i_D0=sink.valid,
i_D1=sink.valid,
i_R=ResetSignal("eth_tx"),
i_S=0
p_DDR_ALIGNMENT = "C0",
p_SRTYPE = "ASYNC",
o_Q = tx_ctl_obuf,
i_C0 = ClockSignal("eth_tx"),
i_C1 = ~ClockSignal("eth_tx"),
i_CE = 1,
i_D0 = sink.valid,
i_D1 = sink.valid,
i_R = ResetSignal("eth_tx"),
i_S = 0
),
Instance("IODELAY2",
p_IDELAY_TYPE="FIXED",
p_ODELAY_VALUE=0,
p_DELAY_SRC="ODATAIN",
o_DOUT=pads.tx_ctl,
i_CAL=0,
i_CE=0,
i_CLK=0,
i_IDATAIN=0,
i_INC=0,
i_IOCLK0=0,
i_IOCLK1=0,
i_ODATAIN=tx_ctl_obuf,
i_RST=0,
i_T=0
p_IDELAY_TYPE = "FIXED",
p_ODELAY_VALUE = 0,
p_DELAY_SRC = "ODATAIN",
o_DOUT = pads.tx_ctl,
i_CAL = 0,
i_CE = 0,
i_CLK = 0,
i_IDATAIN = 0,
i_INC = 0,
i_IOCLK0 = 0,
i_IOCLK1 = 0 ,
i_ODATAIN = tx_ctl_obuf,
i_RST = 0,
i_T = 0,
)
]
for i in range(4):
self.specials += [
Instance("ODDR2",
p_DDR_ALIGNMENT="C0",
p_SRTYPE="ASYNC",
o_Q=tx_data_obuf[i],
i_C0=ClockSignal("eth_tx"),
i_C1=~ClockSignal("eth_tx"),
i_CE=1,
i_D0=sink.data[i],
i_D1=sink.data[4+i],
i_R=ResetSignal("eth_tx"),
i_S=0
p_DDR_ALIGNMENT = "C0",
p_SRTYPE = "ASYNC",
o_Q = tx_data_obuf[i],
i_C0 = ClockSignal("eth_tx"),
i_C1 = ~ClockSignal("eth_tx"),
i_CE = 1,
i_D0 = sink.data[i],
i_D1 = sink.data[4+i],
i_R = ResetSignal("eth_tx"),
i_S = 0,
),
Instance("IODELAY2",
p_IDELAY_TYPE="FIXED",
p_ODELAY_VALUE=0,
p_DELAY_SRC="ODATAIN",
o_DOUT=pads.tx_data[i],
i_CAL=0,
i_CE=0,
i_CLK=0,
i_IDATAIN=0,
i_INC=0,
i_IOCLK0=0,
i_IOCLK1=0,
i_ODATAIN=tx_data_obuf[i],
i_RST=0,
i_T=0
p_IDELAY_TYPE = "FIXED",
p_ODELAY_VALUE = 0,
p_DELAY_SRC = "ODATAIN",
o_DOUT = pads.tx_data[i],
i_CAL = 0,
i_CE = 0,
i_CLK = 0,
i_IDATAIN = 0,
i_INC = 0,
i_IOCLK0 = 0,
i_IOCLK1 = 0,
i_ODATAIN = tx_data_obuf[i],
i_RST = 0,
i_T = 0,
)
]
self.comb += sink.ready.eq(1)
@ -102,64 +102,70 @@ class LiteEthPHYRGMIIRX(Module):
rx_data_reg = Signal(8)
self.specials += [
Instance("IBUF", i_I=pads.rx_ctl, o_O=rx_ctl_ibuf),
Instance("IBUF",
i_I = pads.rx_ctl,
o_O = rx_ctl_ibuf,
),
Instance("IODELAY2",
p_IDELAY_TYPE="FIXED",
p_ODELAY_VALUE=rx_delay_taps,
p_DELAY_SRC="IDATAIN",
o_DATAOUT=rx_ctl_idelay,
i_CAL=0,
i_CE=0,
i_CLK=0,
i_IDATAIN=rx_ctl_ibuf,
i_INC=0,
i_IOCLK0=0,
i_IOCLK1=0,
i_ODATAIN=0,
i_RST=0,
i_T=1
p_IDELAY_TYPE = "FIXED",
p_ODELAY_VALUE = rx_delay_taps,
p_DELAY_SRC = "IDATAIN",
o_DATAOUT = rx_ctl_idelay,
i_CAL = 0,
i_CE = 0,
i_CLK = 0,
i_IDATAIN = rx_ctl_ibuf,
i_INC = 0,
i_IOCLK0 = 0,
i_IOCLK1 = 0,
i_ODATAIN = 0,
i_RST = 0,
i_T = 1,
),
Instance("IDDR2",
p_DDR_ALIGNMENT="C0",
o_Q0=rx_ctl,
i_C0=ClockSignal("eth_rx"),
i_C1=~ClockSignal("eth_rx"),
i_CE=1,
i_D=rx_ctl_idelay,
i_R=0,
i_S=0
p_DDR_ALIGNMENT = "C0",
o_Q0 = rx_ctl,
i_C0 = ClockSignal("eth_rx"),
i_C1 = ~ClockSignal("eth_rx"),
i_CE = 1,
i_D = rx_ctl_idelay,
i_R = 0,
i_S = 0,
)
]
self.sync += rx_ctl_reg.eq(rx_ctl)
for i in range(4):
self.specials += [
Instance("IBUF", i_I=pads.rx_data[i], o_O=rx_data_ibuf[i]),
Instance("IBUF",
i_I = pads.rx_data[i],
o_O = rx_data_ibuf[i],
),
Instance("IODELAY2",
p_IDELAY_TYPE="FIXED",
p_ODELAY_VALUE=rx_delay_taps,
p_DELAY_SRC="IDATAIN",
o_DATAOUT=rx_data_idelay[i],
i_CAL=0,
i_CE=0,
i_CLK=0,
i_IDATAIN=rx_data_ibuf[i],
i_INC=0,
i_IOCLK0=0,
i_IOCLK1=0,
i_ODATAIN=0,
i_RST=0,
i_T=1
p_IDELAY_TYPE = "FIXED",
p_ODELAY_VALUE = rx_delay_taps,
p_DELAY_SRC = "IDATAIN",
o_DATAOUT = rx_data_idelay[i],
i_CAL = 0,
i_CE = 0,
i_CLK = 0,
i_IDATAIN = rx_data_ibuf[i],
i_INC = 0,
i_IOCLK0 = 0,
i_IOCLK1 = 0,
i_ODATAIN = 0,
i_RST = 0,
i_T = 1,
),
Instance("IDDR2",
p_DDR_ALIGNMENT="C0",
o_Q0=rx_data[i],
o_Q1=rx_data[i+4],
i_C0=ClockSignal("eth_rx"),
i_C1=~ClockSignal("eth_rx"),
i_CE=1,
i_D=rx_data_idelay[i],
i_R=0,
i_S=0
p_DDR_ALIGNMENT = "C0",
o_Q0 = rx_data[i],
o_Q1 = rx_data[i+4],
i_C0 = ClockSignal("eth_rx"),
i_C1 = ~ClockSignal("eth_rx"),
i_CE = 1,
i_D = rx_data_idelay[i],
i_R = 0,
i_S = 0,
)
]
self.sync += rx_data_reg.eq(rx_data)
@ -190,8 +196,14 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR):
# RX
eth_rx_clk_ibuf = Signal()
self.specials += [
Instance("IBUF", i_I=clock_pads.rx, o_O=eth_rx_clk_ibuf),
Instance("BUFG", i_I=eth_rx_clk_ibuf, o_O=self.cd_eth_rx.clk)
Instance("IBUF",
i_I = clock_pads.rx,
o_O = eth_rx_clk_ibuf,
),
Instance("BUFG",
i_I = eth_rx_clk_ibuf,
o_O = self.cd_eth_rx.clk,
),
]
# TX
@ -201,32 +213,32 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR):
eth_tx_clk_o = Signal()
self.specials += [
Instance("ODDR2",
p_DDR_ALIGNMENT="C0",
p_SRTYPE="ASYNC",
o_Q=eth_tx_clk_o,
i_C0=ClockSignal("eth_tx"),
i_C1=~ClockSignal("eth_tx"),
i_CE=1,
i_D0=1,
i_D1=0,
i_R=ResetSignal("eth_tx"),
i_S=0
p_DDR_ALIGNMENT = "C0",
p_SRTYPE = "ASYNC",
o_Q = eth_tx_clk_o,
i_C0 = ClockSignal("eth_tx"),
i_C1 = ~ClockSignal("eth_tx"),
i_CE = 1,
i_D0 = 1,
i_D1 = 0,
i_R = ResetSignal("eth_tx"),
i_S = 0,
),
Instance("IODELAY2",
p_IDELAY_TYPE="FIXED",
p_ODELAY_VALUE=tx_delay_taps,
p_DELAY_SRC="ODATAIN",
o_DOUT=clock_pads.tx,
i_CAL=0,
i_CE=0,
i_CLK=0,
i_IDATAIN=0,
i_INC=0,
i_IOCLK0=0,
i_IOCLK1=0,
i_ODATAIN=eth_tx_clk_o,
i_RST=0,
i_T=0
p_IDELAY_TYPE = "FIXED",
p_ODELAY_VALUE = tx_delay_taps,
p_DELAY_SRC = "ODATAIN",
o_DOUT = clock_pads.tx,
i_CAL = 0,
i_CE = 0,
i_CLK = 0,
i_IDATAIN = 0,
i_INC = 0,
i_IOCLK0 = 0,
i_IOCLK1 = 0,
i_ODATAIN = eth_tx_clk_o,
i_RST = 0,
i_T = 0,
)
]

109
liteeth/phy/s7rgmii.py
View File

@ -21,20 +21,36 @@ class LiteEthPHYRGMIITX(Module):
self.specials += [
Instance("ODDR",
p_DDR_CLK_EDGE="SAME_EDGE",
i_C=ClockSignal("eth_tx"), i_CE=1, i_S=0, i_R=0,
i_D1=sink.valid, i_D2=sink.valid, o_Q=tx_ctl_obuf
p_DDR_CLK_EDGE = "SAME_EDGE",
i_C = ClockSignal("eth_tx"),
i_CE = 1,
i_S = 0,
i_R = 0,
i_D1 = sink.valid,
i_D2 = sink.valid,
o_Q = tx_ctl_obuf,
),
Instance("OBUF",
i_I = tx_ctl_obuf,
o_O = pads.tx_ctl,
),
Instance("OBUF", i_I=tx_ctl_obuf, o_O=pads.tx_ctl)
]
for i in range(4):
self.specials += [
Instance("ODDR",
p_DDR_CLK_EDGE="SAME_EDGE",
i_C=ClockSignal("eth_tx"), i_CE=1, i_S=0, i_R=0,
i_D1=sink.data[i], i_D2=sink.data[4+i], o_Q=tx_data_obuf[i],
p_DDR_CLK_EDGE = "SAME_EDGE",
i_C = ClockSignal("eth_tx"),
i_CE = 1,
i_S = 0,
i_R = 0,
i_D1 = sink.data[i],
i_D2 = sink.data[4+i],
o_Q = tx_data_obuf[i],
),
Instance("OBUF", i_I=tx_data_obuf[i], o_O=pads.tx_data[i])
Instance("OBUF",
i_I = tx_data_obuf[i],
o_O = pads.tx_data[i],
)
]
self.comb += sink.ready.eq(1)
@ -58,28 +74,53 @@ class LiteEthPHYRGMIIRX(Module):
self.specials += [
Instance("IBUF", i_I=pads.rx_ctl, o_O=rx_ctl_ibuf),
Instance("IDELAYE2",
p_IDELAY_TYPE="FIXED", p_IDELAY_VALUE=rx_delay_taps,
i_C=0, i_LD=0, i_CE=0, i_LDPIPEEN=0, i_INC=0,
i_IDATAIN=rx_ctl_ibuf, o_DATAOUT=rx_ctl_idelay
p_IDELAY_TYPE = "FIXED",
p_IDELAY_VALUE = rx_delay_taps,
i_C = 0,
i_LD = 0,
i_CE = 0,
i_LDPIPEEN = 0,
i_INC = 0,
i_IDATAIN = rx_ctl_ibuf,
o_DATAOUT = rx_ctl_idelay,
),
Instance("IDDR",
p_DDR_CLK_EDGE="SAME_EDGE_PIPELINED",
i_C=ClockSignal("eth_rx"), i_CE=1, i_S=0, i_R=0,
i_D=rx_ctl_idelay, o_Q1=rx_ctl, #o_Q2=,
p_DDR_CLK_EDGE = "SAME_EDGE_PIPELINED",
i_C = ClockSignal("eth_rx"),
i_CE = 1,
i_S = 0,
i_R = 0,
i_D = rx_ctl_idelay,
o_Q1 = rx_ctl,
o_Q2 = Signal(),
)
]
for i in range(4):
self.specials += [
Instance("IBUF", i_I=pads.rx_data[i], o_O=rx_data_ibuf[i]),
Instance("IBUF",
i_I = pads.rx_data[i],
o_O = rx_data_ibuf[i],
),
Instance("IDELAYE2",
p_IDELAY_TYPE="FIXED", p_IDELAY_VALUE=rx_delay_taps,
i_C=0, i_LD=0, i_CE=0, i_LDPIPEEN=0, i_INC=0,
i_IDATAIN=rx_data_ibuf[i], o_DATAOUT=rx_data_idelay[i]
p_IDELAY_TYPE = "FIXED",
p_IDELAY_VALUE = rx_delay_taps,
i_C = 0,
i_LD = 0,
i_CE = 0,
i_LDPIPEEN = 0,
i_INC = 0,
i_IDATAIN = rx_data_ibuf[i],
o_DATAOUT = rx_data_idelay[i],
),
Instance("IDDR",
p_DDR_CLK_EDGE="SAME_EDGE_PIPELINED",
i_C=ClockSignal("eth_rx"), i_CE=1, i_S=0, i_R=0,
i_D=rx_data_idelay[i], o_Q1=rx_data[i], o_Q2=rx_data[i+4],
p_DDR_CLK_EDGE = "SAME_EDGE_PIPELINED",
i_C = ClockSignal("eth_rx"),
i_CE = 1,
i_S = 0,
i_R = 0,
i_D = rx_data_idelay[i],
o_Q1 = rx_data[i],
o_Q2 = rx_data[i+4],
)
]
@ -108,8 +149,14 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR):
# RX
eth_rx_clk_ibuf = Signal()
self.specials += [
Instance("IBUF", i_I=clock_pads.rx, o_O=eth_rx_clk_ibuf),
Instance("BUFG", i_I=eth_rx_clk_ibuf, o_O=self.cd_eth_rx.clk)
Instance("IBUF",
i_I = clock_pads.rx,
o_O = eth_rx_clk_ibuf,
),
Instance("BUFG",
i_I = eth_rx_clk_ibuf,
o_O = self.cd_eth_rx.clk,
),
]
# TX
@ -124,11 +171,19 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR):
eth_tx_clk_obuf = Signal()
self.specials += [
Instance("ODDR",
p_DDR_CLK_EDGE="SAME_EDGE",
i_C=ClockSignal("eth_tx_delayed"), i_CE=1, i_S=0, i_R=0,
i_D1=1, i_D2=0, o_Q=eth_tx_clk_obuf
p_DDR_CLK_EDGE = "SAME_EDGE",
i_C = ClockSignal("eth_tx_delayed"),
i_CE = 1,
i_S = 0,
i_R = 0,
i_D1 = 1,
i_D2 = 0,
o_Q = eth_tx_clk_obuf,
),
Instance("OBUF", i_I=eth_tx_clk_obuf, o_O=clock_pads.tx)
Instance("OBUF",
i_I = eth_tx_clk_obuf,
o_O = clock_pads.tx,
)
]
# Reset

169
liteeth/phy/usrgmii.py
View File

@ -21,14 +21,15 @@ class LiteEthPHYRGMIITX(Module):
self.specials += [
Instance("ODDRE1",
i_C=ClockSignal("eth_tx"),
i_SR=0,
i_D1=sink.valid,
i_D2=sink.valid,
o_Q=tx_ctl_obuf),
i_C = ClockSignal("eth_tx"),
i_SR = 0,
i_D1 = sink.valid,
i_D2 = sink.valid,
o_Q = tx_ctl_obuf),
Instance("OBUF",
i_I=tx_ctl_obuf,
o_O=pads.tx_ctl)
i_I = tx_ctl_obuf,
o_O = pads.tx_ctl,
),
]
for i in range(4):
self.specials += [
@ -37,10 +38,12 @@ class LiteEthPHYRGMIITX(Module):
i_SR=0,
i_D1=sink.data[i],
i_D2=sink.data[4 + i],
o_Q=tx_data_obuf[i]),
o_Q=tx_data_obuf[i],
),
Instance("OBUF",
i_I=tx_data_obuf[i],
o_O=pads.tx_data[i])
o_O=pads.tx_data[i],
),
]
self.comb += sink.ready.eq(1)
@ -59,69 +62,79 @@ class LiteEthPHYRGMIIRX(Module):
rx_data = Signal(8)
self.specials += [
Instance("IBUF", i_I=pads.rx_ctl, o_O=rx_ctl_ibuf),
Instance("IBUF",
i_I=pads.rx_ctl,
o_O=rx_ctl_ibuf
),
Instance("IDELAYE3",
p_DELAY_SRC="IDATAIN",
p_CASCADE="NONE",
p_DELAY_TYPE="FIXED",
p_DELAY_VALUE=int(rx_delay*1e12),
p_REFCLK_FREQUENCY=300.0,
p_DELAY_FORMAT="TIME",
p_UPDATE_MODE="ASYNC",
i_CASC_IN=0,
i_CASC_RETURN=0,
i_CE=0,
i_CLK=0,
i_INC=0,
i_LOAD=0,
i_CNTVALUEIN=0,
i_IDATAIN=rx_ctl_ibuf,
i_RST=0,
i_EN_VTC=1,
o_DATAOUT=rx_ctl_idelay),
p_DELAY_SRC = "IDATAIN",
p_CASCADE = "NONE",
p_DELAY_TYPE = "FIXED",
p_DELAY_VALUE = int(rx_delay*1e12),
p_REFCLK_FREQUENCY = 300.0,
p_DELAY_FORMAT = "TIME",
p_UPDATE_MODE = "ASYNC",
i_CASC_IN = 0,
i_CASC_RETURN = 0,
i_CE = 0,
i_CLK = 0,
i_INC = 0,
i_LOAD = 0,
i_CNTVALUEIN = 0,
i_IDATAIN = rx_ctl_ibuf,
i_RST = 0,
i_EN_VTC = 1,
o_DATAOUT = rx_ctl_idelay,
),
Instance("IDDRE1",
p_DDR_CLK_EDGE="SAME_EDGE_PIPELINED",
p_IS_C_INVERTED=0,
p_IS_CB_INVERTED=1,
i_C=ClockSignal("eth_rx"),
i_CB=ClockSignal("eth_rx"),
i_R=0,
i_D=rx_ctl_idelay,
o_Q1=rx_ctl,
o_Q2=Signal())
p_DDR_CLK_EDGE = "SAME_EDGE_PIPELINED",
p_IS_C_INVERTED = 0,
p_IS_CB_INVERTED = 1,
i_C = ClockSignal("eth_rx"),
i_CB = ClockSignal("eth_rx"),
i_R = 0,
i_D = rx_ctl_idelay,
o_Q1 = rx_ctl,
o_Q2 = Signal(),
),
]
for i in range(4):
self.specials += [
Instance("IBUF", i_I=pads.rx_data[i], o_O=rx_data_ibuf[i]),
Instance("IBUF",
i_I = pads.rx_data[i],
o_O = rx_data_ibuf[i],
),
Instance("IDELAYE3",
p_DELAY_SRC="IDATAIN",
p_CASCADE="NONE",
p_DELAY_TYPE="FIXED",
p_DELAY_VALUE=int(rx_delay*1e12),
p_REFCLK_FREQUENCY=300.0,
p_UPDATE_MODE="ASYNC",
p_DELAY_FORMAT="TIME",
i_CASC_IN=0,
i_CASC_RETURN=0,
i_CE=0,
i_CLK=0,
i_INC=0,
i_LOAD=0,
i_CNTVALUEIN=0,
i_IDATAIN=rx_data_ibuf[i],
i_RST=0,
i_EN_VTC=1,
o_DATAOUT=rx_data_idelay[i]),
p_DELAY_SRC = "IDATAIN",
p_CASCADE = "NONE",
p_DELAY_TYPE = "FIXED",
p_DELAY_VALUE = int(rx_delay*1e12),
p_REFCLK_FREQUENCY = 300.0,
p_UPDATE_MODE = "ASYNC",
p_DELAY_FORMAT = "TIME",
i_CASC_IN = 0,
i_CASC_RETURN = 0,
i_CE = 0,
i_CLK = 0,
i_INC = 0,
i_LOAD = 0,
i_CNTVALUEIN = 0,
i_IDATAIN = rx_data_ibuf[i],
i_RST = 0,
i_EN_VTC = 1,
o_DATAOUT = rx_data_idelay[i],
),
Instance("IDDRE1",
p_DDR_CLK_EDGE="SAME_EDGE_PIPELINED",
p_IS_C_INVERTED=0,
p_IS_CB_INVERTED=1,
i_C=ClockSignal("eth_rx"),
i_CB=ClockSignal("eth_rx"),
i_R=0,
i_D=rx_data_idelay[i],
o_Q1=rx_data[i],
o_Q2=rx_data[i + 4])
p_DDR_CLK_EDGE = "SAME_EDGE_PIPELINED",
p_IS_C_INVERTED = 0,
p_IS_CB_INVERTED = 1,
i_C = ClockSignal("eth_rx"),
i_CB = ClockSignal("eth_rx"),
i_R = 0,
i_D = rx_data_idelay[i],
o_Q1 = rx_data[i],
o_Q2 = rx_data[i + 4],
),
]
rx_ctl_d = Signal()
@ -149,8 +162,14 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR):
# RX
eth_rx_clk_ibuf = Signal()
self.specials += [
Instance("IBUF", i_I=clock_pads.rx, o_O=eth_rx_clk_ibuf),
Instance("BUFG", i_I=eth_rx_clk_ibuf, o_O=self.cd_eth_rx.clk)
Instance("IBUF",
i_I = clock_pads.rx,
o_O = eth_rx_clk_ibuf,
),
Instance("BUFG",
i_I = eth_rx_clk_ibuf,
o_O = self.cd_eth_rx.clk,
)
]
# TX
@ -165,12 +184,16 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR):
eth_tx_clk_obuf = Signal()
self.specials += [
Instance("ODDRE1",
i_C=ClockSignal("eth_tx_delayed"),
i_SR=0,
i_D1=1,
i_D2=0,
o_Q=eth_tx_clk_obuf),
Instance("OBUF", i_I=eth_tx_clk_obuf, o_O=clock_pads.tx)
i_C = ClockSignal("eth_tx_delayed"),
i_SR = 0,
i_D1 = 1,
i_D2 = 0,
o_Q = eth_tx_clk_obuf
),
Instance("OBUF",
i_I = eth_tx_clk_obuf,
o_O = clock_pads.tx,
)
]
# Reset