diff --git a/example_designs/targets/etherbone.py b/example_designs/targets/etherbone.py index b3dec12..73fbc6d 100644 --- a/example_designs/targets/etherbone.py +++ b/example_designs/targets/etherbone.py @@ -1,7 +1,7 @@ from liteeth.common import * +from liteeth.frontend.etherbone import LiteEthEtherbone from targets.base import BaseSoC -from liteeth.frontend.etherbone import LiteEthEtherbone class EtherboneSoC(BaseSoC): diff --git a/example_designs/targets/tty.py b/example_designs/targets/tty.py index 00d1202..3e3713f 100644 --- a/example_designs/targets/tty.py +++ b/example_designs/targets/tty.py @@ -1,7 +1,7 @@ from liteeth.common import * +from liteeth.frontend.tty import LiteEthTTY from targets.base import BaseSoC -from liteeth.frontend.tty import LiteEthTTY class TTYSoC(BaseSoC): diff --git a/example_designs/targets/udp.py b/example_designs/targets/udp.py index ab62acd..d85c2d3 100644 --- a/example_designs/targets/udp.py +++ b/example_designs/targets/udp.py @@ -1,5 +1,7 @@ from liteeth.common import * +from litex.soc.interconnect.stream_packet import Buffer + from targets.base import BaseSoC diff --git a/liteeth/common.py b/liteeth/common.py index 83f6982..e911e1b 100644 --- a/liteeth/common.py +++ b/liteeth/common.py @@ -1,16 +1,12 @@ -import math -from collections import OrderedDict +from math import ceil from litex.gen import * -from litex.gen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen.genlib.record import * -from litex.gen.genlib.fsm import FSM, NextState -from litex.gen.genlib.misc import chooser, WaitTimer from litex.soc.interconnect.stream import * -from litex.soc.interconnect.stream_packet import * from litex.soc.interconnect.csr import * +from litex.soc.interconnect.stream_packet import Header, HeaderField + def reverse_bytes(signal): n = (len(signal)+7)//8 diff --git a/liteeth/core/arp.py b/liteeth/core/arp.py index 1f136f5..b2644ad 100644 --- a/liteeth/core/arp.py +++ b/liteeth/core/arp.py @@ -1,5 +1,8 @@ from liteeth.common import * +from litex.gen.genlib.misc import WaitTimer +from litex.soc.interconnect.stream_packet import Depacketizer, Packetizer + _arp_table_layout = [ ("reply", 1), diff --git a/liteeth/core/icmp.py b/liteeth/core/icmp.py index 85bf796..34bfbdc 100644 --- a/liteeth/core/icmp.py +++ b/liteeth/core/icmp.py @@ -1,5 +1,8 @@ from liteeth.common import * +from litex.soc.interconnect.stream_packet import Depacketizer, Packetizer, Buffer + + # icmp tx class LiteEthICMPPacketizer(Packetizer): diff --git a/liteeth/core/ip.py b/liteeth/core/ip.py index 05c102b..6e51833 100644 --- a/liteeth/core/ip.py +++ b/liteeth/core/ip.py @@ -1,6 +1,9 @@ from liteeth.common import * from liteeth.crossbar import LiteEthCrossbar +from litex.soc.interconnect.stream_packet import Depacketizer, Packetizer + + # ip crossbar class LiteEthIPV4MasterPort: diff --git a/liteeth/core/mac/common.py b/liteeth/core/mac/common.py index 64d6424..cf147f6 100644 --- a/liteeth/core/mac/common.py +++ b/liteeth/core/mac/common.py @@ -1,6 +1,8 @@ from liteeth.common import * from liteeth.crossbar import LiteEthCrossbar +from litex.soc.interconnect.stream_packet import Depacketizer, Packetizer + class LiteEthMACDepacketizer(Depacketizer): def __init__(self): diff --git a/liteeth/core/mac/core/crc.py b/liteeth/core/mac/core/crc.py index bd24c26..a36fefd 100644 --- a/liteeth/core/mac/core/crc.py +++ b/liteeth/core/mac/core/crc.py @@ -1,7 +1,10 @@ -from liteeth.common import * from functools import reduce from operator import xor +from collections import OrderedDict +from liteeth.common import * + +from litex.gen.genlib.misc import chooser, WaitTimer class LiteEthMACCRCEngine(Module): diff --git a/liteeth/core/mac/core/gap.py b/liteeth/core/mac/core/gap.py index 905d89e..8b5f516 100644 --- a/liteeth/core/mac/core/gap.py +++ b/liteeth/core/mac/core/gap.py @@ -7,7 +7,7 @@ class LiteEthMACGap(Module): # # # - gap = math.ceil(eth_interpacket_gap/(dw//8)) + gap = ceil(eth_interpacket_gap/(dw//8)) counter = Signal(max=gap) counter_reset = Signal() counter_ce = Signal() diff --git a/liteeth/core/mac/core/padding.py b/liteeth/core/mac/core/padding.py index 3aa8939..d1f4885 100644 --- a/liteeth/core/mac/core/padding.py +++ b/liteeth/core/mac/core/padding.py @@ -8,7 +8,7 @@ class LiteEthMACPaddingInserter(Module): # # # - padding_limit = math.ceil(padding/(dw/8))-1 + padding_limit = ceil(padding/(dw/8))-1 counter = Signal(16, reset=1) counter_done = Signal() diff --git a/liteeth/core/mac/core/preamble.py b/liteeth/core/mac/core/preamble.py index 2160c0c..149e720 100644 --- a/liteeth/core/mac/core/preamble.py +++ b/liteeth/core/mac/core/preamble.py @@ -1,5 +1,7 @@ from liteeth.common import * +from litex.gen.genlib.misc import chooser + class LiteEthMACPreambleInserter(Module): def __init__(self, dw): diff --git a/liteeth/core/udp.py b/liteeth/core/udp.py index fa30a20..56d1cf2 100644 --- a/liteeth/core/udp.py +++ b/liteeth/core/udp.py @@ -1,6 +1,9 @@ from liteeth.common import * from liteeth.crossbar import LiteEthCrossbar +from litex.soc.interconnect.stream_packet import Depacketizer, Packetizer, Buffer + + # udp crossbar class LiteEthUDPMasterPort: diff --git a/liteeth/crossbar.py b/liteeth/crossbar.py index bf61ec4..321fb62 100644 --- a/liteeth/crossbar.py +++ b/liteeth/crossbar.py @@ -2,6 +2,9 @@ from collections import OrderedDict from liteeth.common import * +from litex.soc.interconnect.stream_packet import Arbiter, Dispatcher + + class LiteEthCrossbar(Module): def __init__(self, master_port, dispatch_param): self.users = OrderedDict() diff --git a/liteeth/frontend/etherbone.py b/liteeth/frontend/etherbone.py index d3dbca5..9645609 100644 --- a/liteeth/frontend/etherbone.py +++ b/liteeth/frontend/etherbone.py @@ -1,6 +1,7 @@ from liteeth.common import * from litex.soc.interconnect import wishbone +from litex.soc.interconnect.stream_packet import * # etherbone packet diff --git a/liteeth/phy/gmii.py b/liteeth/phy/gmii.py index 46e6d93..10c72c0 100644 --- a/liteeth/phy/gmii.py +++ b/liteeth/phy/gmii.py @@ -1,7 +1,8 @@ -from litex.gen.genlib.io import DDROutput - from liteeth.common import * +from litex.gen.genlib.io import DDROutput +from litex.gen.genlib.resetsync import AsyncResetSynchronizer + class LiteEthPHYGMIITX(Module): def __init__(self, pads, pads_register=True): diff --git a/liteeth/phy/gmii_mii.py b/liteeth/phy/gmii_mii.py index 1b5613f..b003966 100644 --- a/liteeth/phy/gmii_mii.py +++ b/liteeth/phy/gmii_mii.py @@ -1,12 +1,13 @@ +from liteeth.common import * +from liteeth.phy.gmii import LiteEthPHYGMIICRG +from liteeth.phy.mii import LiteEthPHYMIITX, LiteEthPHYMIIRX +from liteeth.phy.gmii import LiteEthPHYGMIITX, LiteEthPHYGMIIRX + from litex.gen.genlib.io import DDROutput from litex.gen.genlib.cdc import PulseSynchronizer from litex.soc.interconnect.stream import Multiplexer, Demultiplexer -from liteeth.common import * -from liteeth.phy.gmii import LiteEthPHYGMIICRG -from liteeth.phy.mii import LiteEthPHYMIITX, LiteEthPHYMIIRX -from liteeth.phy.gmii import LiteEthPHYGMIITX, LiteEthPHYGMIIRX modes = { "GMII": 0, diff --git a/liteeth/phy/mii.py b/liteeth/phy/mii.py index 8363623..a140c18 100644 --- a/liteeth/phy/mii.py +++ b/liteeth/phy/mii.py @@ -1,5 +1,7 @@ from liteeth.common import * +from litex.gen.genlib.resetsync import AsyncResetSynchronizer + def converter_description(dw): payload_layout = [("data", dw)] diff --git a/liteeth/phy/rmii.py b/liteeth/phy/rmii.py index bb812e9..d3590ce 100644 --- a/liteeth/phy/rmii.py +++ b/liteeth/phy/rmii.py @@ -1,5 +1,7 @@ from liteeth.common import * +from litex.gen.genlib.resetsync import AsyncResetSynchronizer + def converter_description(dw): payload_layout = [("data", dw)] diff --git a/liteeth/phy/s6rgmii.py b/liteeth/phy/s6rgmii.py index 8f7eaa9..d3d49d6 100644 --- a/liteeth/phy/s6rgmii.py +++ b/liteeth/phy/s6rgmii.py @@ -1,10 +1,11 @@ # RGMII PHY for Spartan-6 +from liteeth.common import * from litex.gen.genlib.io import DDROutput from litex.gen.genlib.misc import WaitTimer from litex.gen.genlib.fsm import FSM, NextState -from liteeth.common import * +from litex.gen.genlib.resetsync import AsyncResetSynchronizer class LiteEthPHYRGMIITX(Module):