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mac/core: Improve timing closure of core 

On ECP5 targets the core struggles to meet timing closure. This
change adds buffers to the CRC module on tx/rx paths.
This results in 20-30MHz gain to max clock rate.

This fixes #47
This commit is contained in:
Greg Davill 2020-10-11 14:46:16 +10:30
parent 54acf9fd76
commit 9aee36939f
1 changed files with 4 additions and 2 deletions
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6
liteeth/mac/core.py
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@ -12,6 +12,8 @@ from liteeth.phy.model import LiteEthPHYModel
from migen.genlib.cdc import PulseSynchronizer
from litex.soc.interconnect.stream import BufferizeEndpoints, DIR_SOURCE, DIR_SINK
# MAC Core -----------------------------------------------------------------------------------------
class LiteEthMACCore(Module, AutoCSR):
@ -44,8 +46,8 @@ class LiteEthMACCore(Module, AutoCSR):
self.submodules += ClockDomainsRenamer("eth_rx")(preamble_checker)
# CRC insert/check
crc32_inserter = crc.LiteEthMACCRC32Inserter(eth_phy_description(phy.dw))
crc32_checker = crc.LiteEthMACCRC32Checker(eth_phy_description(phy.dw))
crc32_inserter = BufferizeEndpoints({"sink": DIR_SINK})(crc.LiteEthMACCRC32Inserter(eth_phy_description(phy.dw)))
crc32_checker = BufferizeEndpoints({"sink": DIR_SINK})(crc.LiteEthMACCRC32Checker(eth_phy_description(phy.dw)))
self.submodules += ClockDomainsRenamer("eth_tx")(crc32_inserter)
self.submodules += ClockDomainsRenamer("eth_rx")(crc32_checker)