From 9aee36939f23855e231e3bd85de83c6cf45553cb Mon Sep 17 00:00:00 2001 From: Greg Davill Date: Sun, 11 Oct 2020 14:46:16 +1030 Subject: [PATCH] mac/core: Improve timing closure of core On ECP5 targets the core struggles to meet timing closure. This change adds buffers to the CRC module on tx/rx paths. This results in 20-30MHz gain to max clock rate. This fixes #47 --- liteeth/mac/core.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/liteeth/mac/core.py b/liteeth/mac/core.py index e773bba..e4b107c 100644 --- a/liteeth/mac/core.py +++ b/liteeth/mac/core.py @@ -12,6 +12,8 @@ from liteeth.phy.model import LiteEthPHYModel from migen.genlib.cdc import PulseSynchronizer +from litex.soc.interconnect.stream import BufferizeEndpoints, DIR_SOURCE, DIR_SINK + # MAC Core ----------------------------------------------------------------------------------------- class LiteEthMACCore(Module, AutoCSR): @@ -44,8 +46,8 @@ class LiteEthMACCore(Module, AutoCSR): self.submodules += ClockDomainsRenamer("eth_rx")(preamble_checker) # CRC insert/check - crc32_inserter = crc.LiteEthMACCRC32Inserter(eth_phy_description(phy.dw)) - crc32_checker = crc.LiteEthMACCRC32Checker(eth_phy_description(phy.dw)) + crc32_inserter = BufferizeEndpoints({"sink": DIR_SINK})(crc.LiteEthMACCRC32Inserter(eth_phy_description(phy.dw))) + crc32_checker = BufferizeEndpoints({"sink": DIR_SINK})(crc.LiteEthMACCRC32Checker(eth_phy_description(phy.dw))) self.submodules += ClockDomainsRenamer("eth_tx")(crc32_inserter) self.submodules += ClockDomainsRenamer("eth_rx")(crc32_checker)