From 9b38fd8df357e17d65f6f579422de61da2059377 Mon Sep 17 00:00:00 2001 From: Leon Schuermann Date: Sun, 15 Aug 2021 11:12:49 +0200 Subject: [PATCH] mac/preamble: Fix inserter to work for 64 bit On vivado at least Co-authored-by: David Sawatzke --- liteeth/mac/preamble.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/liteeth/mac/preamble.py b/liteeth/mac/preamble.py index 061b41c..85e5dc7 100644 --- a/liteeth/mac/preamble.py +++ b/liteeth/mac/preamble.py @@ -46,7 +46,11 @@ class LiteEthMACPreambleInserter(Module): ) fsm.act("PREAMBLE", self.source.valid.eq(1), - chooser(preamble, count, self.source.data), + # Separate `n` is required as for 64-bit the chooser-statements' + # generated Verilog will otherwise contain a statement which reads + # beyond the bounds of preamble. This is in a branch which can never + # be valid, but is enough reason for Vivado to refuse synthesis. + chooser(preamble, count, self.source.data, n=64//dw), If(self.source.ready, If(count == (64//dw)-1, NextState("COPY")