From 9f698506974f34354723423c99b692d47a0ed8fc Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 13 Jun 2023 17:44:12 +0200
Subject: [PATCH] usp_gth_1000basex: Working :), remove debug.

---
 bench/xu8_st1.py                 |  8 ++++----
 liteeth/phy/usp_gth_1000basex.py | 17 -----------------
 2 files changed, 4 insertions(+), 21 deletions(-)

diff --git a/bench/xu8_st1.py b/bench/xu8_st1.py
index 3f9ed63..8484e21 100755
--- a/bench/xu8_st1.py
+++ b/bench/xu8_st1.py
@@ -48,7 +48,7 @@ class _CRG(LiteXModule):
         self.pll = pll = USMMCM(speedgrade=-1)
         pll.register_clkin(platform.request("clk100"), 100e6)
         pll.create_clkout(self.cd_sys, sys_clk_freq)
-        pll.create_clkout(self.cd_eth, 200e6, buf=None)
+        pll.create_clkout(self.cd_eth, 200e6)
 
 # Bench SoC ----------------------------------------------------------------------------------------
 
@@ -64,10 +64,10 @@ class BenchSoC(SoCCore):
         )
 
         # CRG --------------------------------------------------------------------------------------
-        self.submodules.crg = _CRG(platform, sys_clk_freq)
+        self.crg = _CRG(platform, sys_clk_freq)
 
         # Etherbone --------------------------------------------------------------------------------
-        self.submodules.ethphy = USP_GTH_1000BASEX(self.crg.cd_eth.clk,
+        self.ethphy = USP_GTH_1000BASEX(self.crg.cd_eth.clk,
             data_pads    = self.platform.request("sfp", 0),
             sys_clk_freq = self.clk_freq)
         self.add_etherbone(phy=self.ethphy, buffer_depth=4)
@@ -77,7 +77,7 @@ class BenchSoC(SoCCore):
 
         # Leds -------------------------------------------------------------------------------------
         from litex.soc.cores.led import LedChaser
-        self.submodules.leds = LedChaser(
+        self.leds = LedChaser(
             pads         = platform.request_all("user_led"),
             sys_clk_freq = sys_clk_freq
         )
diff --git a/liteeth/phy/usp_gth_1000basex.py b/liteeth/phy/usp_gth_1000basex.py
index 22fedc0..f81c858 100644
--- a/liteeth/phy/usp_gth_1000basex.py
+++ b/liteeth/phy/usp_gth_1000basex.py
@@ -5,8 +5,6 @@
 # Copyright (c) 2018 Sebastien Bourdeauducq <sb@m-labs.hk>
 # SPDX-License-Identifier: BSD-2-Clause
 
-# Work-In-Progress...
-
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 from migen.genlib.cdc import PulseSynchronizer
@@ -941,18 +939,3 @@ class USP_GTH_1000BASEX(LiteXModule):
             gearbox.tx_data.eq(pcs.tbi_tx),
             pcs.tbi_rx.eq(gearbox.rx_data)
         ]
-
-        self.debug = [
-            gtpowergood,
-            pll_reset,
-            pll_locked,
-            tx_reset,
-            tx_data,
-            tx_reset_done,
-            rx_reset,
-            rx_data,
-            rx_reset_done,
-            self.sink,
-            self.source,
-            self.link_up
-        ]