usp_gth_1000basex: Working :), remove debug.
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@ -48,7 +48,7 @@ class _CRG(LiteXModule):
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self.pll = pll = USMMCM(speedgrade=-1)
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self.pll = pll = USMMCM(speedgrade=-1)
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pll.register_clkin(platform.request("clk100"), 100e6)
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pll.register_clkin(platform.request("clk100"), 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_eth, 200e6, buf=None)
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pll.create_clkout(self.cd_eth, 200e6)
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# Bench SoC ----------------------------------------------------------------------------------------
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# Bench SoC ----------------------------------------------------------------------------------------
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@ -64,10 +64,10 @@ class BenchSoC(SoCCore):
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)
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)
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# CRG --------------------------------------------------------------------------------------
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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self.crg = _CRG(platform, sys_clk_freq)
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# Etherbone --------------------------------------------------------------------------------
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# Etherbone --------------------------------------------------------------------------------
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self.submodules.ethphy = USP_GTH_1000BASEX(self.crg.cd_eth.clk,
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self.ethphy = USP_GTH_1000BASEX(self.crg.cd_eth.clk,
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data_pads = self.platform.request("sfp", 0),
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data_pads = self.platform.request("sfp", 0),
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sys_clk_freq = self.clk_freq)
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sys_clk_freq = self.clk_freq)
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self.add_etherbone(phy=self.ethphy, buffer_depth=4)
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self.add_etherbone(phy=self.ethphy, buffer_depth=4)
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@ -77,7 +77,7 @@ class BenchSoC(SoCCore):
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# Leds -------------------------------------------------------------------------------------
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# Leds -------------------------------------------------------------------------------------
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.led import LedChaser
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self.submodules.leds = LedChaser(
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self.leds = LedChaser(
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pads = platform.request_all("user_led"),
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq
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sys_clk_freq = sys_clk_freq
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)
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)
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@ -5,8 +5,6 @@
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# Copyright (c) 2018 Sebastien Bourdeauducq <sb@m-labs.hk>
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# Copyright (c) 2018 Sebastien Bourdeauducq <sb@m-labs.hk>
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# SPDX-License-Identifier: BSD-2-Clause
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# SPDX-License-Identifier: BSD-2-Clause
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# Work-In-Progress...
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from migen import *
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.genlib.cdc import PulseSynchronizer
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from migen.genlib.cdc import PulseSynchronizer
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@ -941,18 +939,3 @@ class USP_GTH_1000BASEX(LiteXModule):
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gearbox.tx_data.eq(pcs.tbi_tx),
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gearbox.tx_data.eq(pcs.tbi_tx),
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pcs.tbi_rx.eq(gearbox.rx_data)
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pcs.tbi_rx.eq(gearbox.rx_data)
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]
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]
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self.debug = [
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gtpowergood,
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pll_reset,
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pll_locked,
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tx_reset,
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tx_data,
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tx_reset_done,
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rx_reset,
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rx_data,
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rx_reset_done,
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self.sink,
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self.source,
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self.link_up
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]
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