diff --git a/examples/udp_a7_gtp_sgmii.yml b/examples/udp_a7_gtp_sgmii.yml
index f7cf9da..5edc4b5 100644
--- a/examples/udp_a7_gtp_sgmii.yml
+++ b/examples/udp_a7_gtp_sgmii.yml
@@ -5,9 +5,11 @@
 # SPDX-License-Identifier: BSD-2-Clause
 
 # PHY ----------------------------------------------------------------------
-phy       : A7_1000BASEX
-vendor    : xilinx
-toolchain : vivado
+phy             : A7_1000BASEX
+phy_tx_polarity : 0
+phy_rx_polarity : 0
+vendor          : xilinx
+toolchain       : vivado
 
 # Core ---------------------------------------------------------------------
 refclk_freq : 156.25e6
diff --git a/liteeth/gen.py b/liteeth/gen.py
index 7450de0..885e83f 100755
--- a/liteeth/gen.py
+++ b/liteeth/gen.py
@@ -302,8 +302,8 @@ class PHYCore(SoCMini):
                     data_pads    = ethphy_pads,
                     sys_clk_freq = self.clk_freq,
                     with_csr     = False,
-                    rx_polarity  = 0, # Add support to liteeth_gen if useful.
-                    tx_polarity  = 0, # Add support to liteeth_gen if useful.
+                    rx_polarity  = core_config.get("phy_rx_polarity", 0),
+                    tx_polarity  = core_config.get("phy_tx_polarity", 0),
                 )
             # Other 7-Series/Ultrascale(+).
             else:
@@ -313,8 +313,8 @@ class PHYCore(SoCMini):
                     sys_clk_freq       = self.clk_freq,
                     refclk_freq        = core_config.get("refclk_freq", 200e6),
                     with_csr           = False,
-                    rx_polarity        = 0, # Add support to liteeth_gen if useful.
-                    tx_polarity        = 0, # Add support to liteeth_gen if useful.
+                    rx_polarity        = core_config.get("phy_rx_polarity", 0),
+                    tx_polarity        = core_config.get("phy_tx_polarity", 0),
                 )
             self.comb += [
                 ethphy.reset.eq(ethphy_pads.rst),