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liteeth_gen: Add TX/RX polarity support to SGMII/1000BASEX PHYs.

This commit is contained in:
Florent Kermarrec 2024-01-23 12:45:48 +01:00
parent 3b10143da2
commit a00c9a3d22
2 changed files with 9 additions and 7 deletions
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8
examples/udp_a7_gtp_sgmii.yml
View File

@ -5,9 +5,11 @@
# SPDX-License-Identifier: BSD-2-Clause
# PHY ----------------------------------------------------------------------
phy : A7_1000BASEX
vendor : xilinx
toolchain : vivado
phy : A7_1000BASEX
phy_tx_polarity : 0
phy_rx_polarity : 0
vendor : xilinx
toolchain : vivado
# Core ---------------------------------------------------------------------
refclk_freq : 156.25e6

8
liteeth/gen.py
View File

@ -302,8 +302,8 @@ class PHYCore(SoCMini):
data_pads = ethphy_pads,
sys_clk_freq = self.clk_freq,
with_csr = False,
rx_polarity = 0, # Add support to liteeth_gen if useful.
tx_polarity = 0, # Add support to liteeth_gen if useful.
rx_polarity = core_config.get("phy_rx_polarity", 0),
tx_polarity = core_config.get("phy_tx_polarity", 0),
)
# Other 7-Series/Ultrascale(+).
else:
@ -313,8 +313,8 @@ class PHYCore(SoCMini):
sys_clk_freq = self.clk_freq,
refclk_freq = core_config.get("refclk_freq", 200e6),
with_csr = False,
rx_polarity = 0, # Add support to liteeth_gen if useful.
tx_polarity = 0, # Add support to liteeth_gen if useful.
rx_polarity = core_config.get("phy_rx_polarity", 0),
tx_polarity = core_config.get("phy_tx_polarity", 0),
)
self.comb += [
ethphy.reset.eq(ethphy_pads.rst),