From a03216899702459b49fdece2e8d315c66b67e4a8 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 12 Nov 2015 01:45:37 +0100 Subject: [PATCH] start adapting to new migen/litex --- example_designs/make.py | 32 +++++++++------ example_designs/targets/base.py | 21 +++++----- liteeth/common.py | 17 ++++---- liteeth/core/ip.py | 4 +- liteeth/core/mac/core/__init__.py | 28 +++++++------- liteeth/core/mac/core/crc.py | 16 ++++---- liteeth/core/mac/core/gap.py | 16 ++++++-- liteeth/core/mac/core/padding.py | 17 +++++--- liteeth/core/mac/frontend/sram.py | 56 +++++++++++++++++---------- liteeth/core/mac/frontend/wishbone.py | 4 +- liteeth/frontend/etherbone.py | 3 +- liteeth/phy/__init__.py | 4 +- liteeth/phy/gmii.py | 12 +++--- liteeth/phy/gmii_mii.py | 26 ++++++++----- liteeth/phy/mii.py | 6 +-- 15 files changed, 157 insertions(+), 105 deletions(-) diff --git a/example_designs/make.py b/example_designs/make.py index cd15ecc..dcd1c19 100644 --- a/example_designs/make.py +++ b/example_designs/make.py @@ -7,20 +7,31 @@ import subprocess import struct import importlib -from mibuild.tools import write_to_file -from migen.util.misc import autotype -from migen.fhdl import verilog, edif +from migen.fhdl import verilog from migen.fhdl.structure import _Fragment -from migen.bank.description import CSRStatus -from mibuild import tools -from mibuild.xilinx.common import * -from misoclib.soc import cpuif +from litex.build.tools import write_to_file +from litex.build.xilinx.common import * + +from litex.soc.integration import cpu_interface + liteeth_path = "../" sys.path.append(liteeth_path) # XXX from liteeth.common import * +def autotype(s): + if s == "True": + return True + elif s == "False": + return False + try: + return int(s, 0) + except ValueError: + pass + return s + + def _import(default, name): return importlib.import_module(default + "." + name) @@ -55,8 +66,6 @@ all clean, build-csr-csv, build-bitstream, load-bitstream. return parser.parse_args() -# Note: misoclib need to be installed as a python library - if __name__ == "__main__": args = _get_args() @@ -74,7 +83,7 @@ if __name__ == "__main__": raise ValueError("Target has no default platform, specify a platform with -p your_platform") else: platform_name = args.platform - platform_module = _import("mibuild.platforms", platform_name) + platform_module = _import("litex.boards.platforms", platform_name) platform_kwargs = dict((k, autotype(v)) for k, v in args.platform_option) platform = platform_module.Platform(**platform_kwargs) @@ -126,13 +135,12 @@ System Clk: {} MHz if actions["build-bitstream"]: actions["build-csr-csv"] = True - actions["build-bitstream"] = True if actions["clean"]: subprocess.call(["rm", "-rf", "build/*"]) if actions["build-csr-csv"]: - csr_csv = cpuif.get_csr_csv(csr_regions) + csr_csv = cpu_interface.get_csr_csv(csr_regions) write_to_file(args.csr_csv, csr_csv) if actions["build-bitstream"]: diff --git a/example_designs/targets/base.py b/example_designs/targets/base.py index 84d2097..7858846 100644 --- a/example_designs/targets/base.py +++ b/example_designs/targets/base.py @@ -1,31 +1,32 @@ -from migen.bus import wishbone from migen.genlib.io import CRG from migen.fhdl.specials import Keep -from mibuild.xilinx.vivado import XilinxVivadoToolchain -from misoclib.soc import SoC -from misoclib.com.uart.bridge import UARTWishboneBridge +from litex.build.xilinx.vivado import XilinxVivadoToolchain +from litex.soc.interconnect import wishbone + +from litex.soc.integration.soc_core import SoCCore +from litex.soc.cores.uart.bridge import UARTWishboneBridge from liteeth.common import * from liteeth.phy import LiteEthPHY from liteeth.core import LiteEthUDPIPCore -class BaseSoC(SoC): +class BaseSoC(SoCCore): csr_map = { "phy": 11, "core": 12 } - csr_map.update(SoC.csr_map) + csr_map.update(SoCCore.csr_map) def __init__(self, platform, clk_freq=166*1000000, mac_address=0x10e2d5000000, ip_address="192.168.0.42"): clk_freq = int((1/(platform.default_clk_period))*1000000000) - SoC.__init__(self, platform, clk_freq, - cpu_type="none", - with_csr=True, csr_data_width=32, + SoCCore.__init__(self, platform, clk_freq, + cpu_type=None, + csr_data_width=32, with_uart=False, - with_identifier=True, + ident="LiteEth Base Design", with_timer=False ) self.add_cpu_or_bridge(UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200)) diff --git a/liteeth/common.py b/liteeth/common.py index e89d0e1..9c3fd19 100644 --- a/liteeth/common.py +++ b/liteeth/common.py @@ -1,23 +1,22 @@ import math from collections import OrderedDict -from migen.fhdl.std import * +from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer from migen.genlib.record import * from migen.genlib.fsm import FSM, NextState from migen.genlib.misc import chooser, WaitTimer -from migen.flow.actor import * -from migen.actorlib.structuring import Converter, Pipeline -from migen.actorlib.fifo import SyncFIFO, AsyncFIFO -from migen.actorlib.packet import * -from migen.bank.description import * + +from litex.soc.interconnect.stream import * +from litex.soc.interconnect.packet import * +from litex.soc.interconnect.csr import * def reverse_bytes(signal): - n = (flen(signal)+7)//8 + n = (len(signal)+7)//8 r = [] for i in reversed(range(n)): - r.append(signal[i*8:min((i+1)*8, flen(signal))]) + r.append(signal[i*8:min((i+1)*8, len(signal))]) return Cat(*r) @@ -26,7 +25,7 @@ def reverse_bytes(signal): class Counter(Module): def __init__(self, *args, increment=1, **kwargs): self.value = Signal(*args, **kwargs) - self.width = flen(self.value) + self.width = len(self.value) self.sync += self.value.eq(self.value+increment) diff --git a/liteeth/core/ip.py b/liteeth/core/ip.py index 2d4f2ca..05c102b 100644 --- a/liteeth/core/ip.py +++ b/liteeth/core/ip.py @@ -35,8 +35,8 @@ class LiteEthIPV4Crossbar(LiteEthCrossbar): # ip checksum -@DecorateModule(InsertReset) -@DecorateModule(InsertCE) +@ResetInserter() +@CEInserter() class LiteEthIPV4Checksum(Module): def __init__(self, words_per_clock_cycle=1, skip_checksum=False): self.header = Signal(ipv4_header.length*8) diff --git a/liteeth/core/mac/core/__init__.py b/liteeth/core/mac/core/__init__.py index 7a56715..dffeb9d 100644 --- a/liteeth/core/mac/core/__init__.py +++ b/liteeth/core/mac/core/__init__.py @@ -17,8 +17,8 @@ class LiteEthMACCore(Module, AutoCSR): # Interpacket gap tx_gap_inserter = gap.LiteEthMACGap(phy.dw) rx_gap_checker = gap.LiteEthMACGap(phy.dw, ack_on_gap=True) - self.submodules += RenameClockDomains(tx_gap_inserter, "eth_tx") - self.submodules += RenameClockDomains(rx_gap_checker, "eth_rx") + self.submodules += ClockDomainsRenamer("eth_tx")(tx_gap_inserter) + self.submodules += ClockDomainsRenamer("eth_rx")(rx_gap_checker) tx_pipeline += [tx_gap_inserter] rx_pipeline += [rx_gap_checker] @@ -33,14 +33,14 @@ class LiteEthMACCore(Module, AutoCSR): # Preamble insert/check preamble_inserter = preamble.LiteEthMACPreambleInserter(phy.dw) preamble_checker = preamble.LiteEthMACPreambleChecker(phy.dw) - self.submodules += RenameClockDomains(preamble_inserter, "eth_tx") - self.submodules += RenameClockDomains(preamble_checker, "eth_rx") + self.submodules += ClockDomainsRenamer("eth_tx")(preamble_inserter) + self.submodules += ClockDomainsRenamer("eth_rx")(preamble_checker) # CRC insert/check crc32_inserter = crc.LiteEthMACCRC32Inserter(eth_phy_description(phy.dw)) crc32_checker = crc.LiteEthMACCRC32Checker(eth_phy_description(phy.dw)) - self.submodules += RenameClockDomains(crc32_inserter, "eth_tx") - self.submodules += RenameClockDomains(crc32_checker, "eth_rx") + self.submodules += ClockDomainsRenamer("eth_tx")(crc32_inserter) + self.submodules += ClockDomainsRenamer("eth_rx")(crc32_checker) tx_pipeline += [preamble_inserter, crc32_inserter] rx_pipeline += [preamble_checker, crc32_checker] @@ -49,8 +49,8 @@ class LiteEthMACCore(Module, AutoCSR): if with_padding: padding_inserter = padding.LiteEthMACPaddingInserter(phy.dw, 60) padding_checker = padding.LiteEthMACPaddingChecker(phy.dw, 60) - self.submodules += RenameClockDomains(padding_inserter, "eth_tx") - self.submodules += RenameClockDomains(padding_checker, "eth_rx") + self.submodules += ClockDomainsRenamer("eth_tx")(padding_inserter) + self.submodules += ClockDomainsRenamer("eth_rx")(padding_checker) tx_pipeline += [padding_inserter] rx_pipeline += [padding_checker] @@ -59,8 +59,8 @@ class LiteEthMACCore(Module, AutoCSR): if dw != 8: tx_last_be = last_be.LiteEthMACTXLastBE(phy.dw) rx_last_be = last_be.LiteEthMACRXLastBE(phy.dw) - self.submodules += RenameClockDomains(tx_last_be, "eth_tx") - self.submodules += RenameClockDomains(rx_last_be, "eth_rx") + self.submodules += ClockDomainsRenamer("eth_tx")(tx_last_be) + self.submodules += ClockDomainsRenamer("eth_rx")(rx_last_be) tx_pipeline += [tx_last_be] rx_pipeline += [rx_last_be] @@ -74,8 +74,8 @@ class LiteEthMACCore(Module, AutoCSR): rx_converter = Converter(eth_phy_description(phy.dw), eth_phy_description(dw), reverse=reverse) - self.submodules += RenameClockDomains(tx_converter, "eth_tx") - self.submodules += RenameClockDomains(rx_converter, "eth_rx") + self.submodules += ClockDomainsRenamer("eth_tx")(tx_converter) + self.submodules += ClockDomainsRenamer("eth_rx")(rx_converter) tx_pipeline += [tx_converter] rx_pipeline += [rx_converter] @@ -87,8 +87,8 @@ class LiteEthMACCore(Module, AutoCSR): fifo_depth = 64 tx_cdc = AsyncFIFO(eth_phy_description(dw), fifo_depth) rx_cdc = AsyncFIFO(eth_phy_description(dw), fifo_depth) - self.submodules += RenameClockDomains(tx_cdc, {"write": "sys", "read": "eth_tx"}) - self.submodules += RenameClockDomains(rx_cdc, {"write": "eth_rx", "read": "sys"}) + self.submodules += ClockDomainsRenamer({"write": "sys", "read": "eth_tx"})(tx_cdc) + self.submodules += ClockDomainsRenamer({"write": "eth_rx", "read": "sys"})(rx_cdc) tx_pipeline += [tx_cdc] rx_pipeline += [rx_cdc] diff --git a/liteeth/core/mac/core/crc.py b/liteeth/core/mac/core/crc.py index 4765aa7..2daabc2 100644 --- a/liteeth/core/mac/core/crc.py +++ b/liteeth/core/mac/core/crc.py @@ -1,4 +1,7 @@ from liteeth.common import * +from functools import reduce +from operator import xor + class LiteEthMACCRCEngine(Module): @@ -67,11 +70,11 @@ class LiteEthMACCRCEngine(Module): xors += [self.last[n]] elif t == "din": xors += [self.data[n]] - self.comb += self.next[i].eq(optree("^", xors)) + self.comb += self.next[i].eq(reduce(xor, xors)) -@DecorateModule(InsertReset) -@DecorateModule(InsertCE) +@ResetInserter() +@CEInserter() class LiteEthMACCRC32(Module): """IEEE 802.3 CRC @@ -138,7 +141,7 @@ class LiteEthMACCRCInserter(Module): # # # - dw = flen(sink.data) + dw = len(sink.data) crc = crc_class(dw) fsm = FSM(reset_state="IDLE") self.submodules += crc, fsm @@ -219,13 +222,12 @@ class LiteEthMACCRCChecker(Module): # # # - dw = flen(sink.data) + dw = len(sink.data) crc = crc_class(dw) self.submodules += crc ratio = crc.width//dw - error = Signal() - fifo = InsertReset(SyncFIFO(description, ratio + 1)) + fifo = ResetInserter()(SyncFIFO(description, ratio + 1)) self.submodules += fifo fsm = FSM(reset_state="RESET") diff --git a/liteeth/core/mac/core/gap.py b/liteeth/core/mac/core/gap.py index 9935304..905d89e 100644 --- a/liteeth/core/mac/core/gap.py +++ b/liteeth/core/mac/core/gap.py @@ -8,20 +8,28 @@ class LiteEthMACGap(Module): # # # gap = math.ceil(eth_interpacket_gap/(dw//8)) - self.submodules.counter = counter = Counter(max=gap) + counter = Signal(max=gap) + counter_reset = Signal() + counter_ce = Signal() + self.sync += \ + If(counter_reset, + counter.eq(0) + ).Elif(counter_ce, + counter.eq(counter + 1) + ) self.submodules.fsm = fsm = FSM(reset_state="COPY") fsm.act("COPY", - counter.reset.eq(1), + counter_reset.eq(1), Record.connect(sink, source), If(sink.stb & sink.eop & sink.ack, NextState("GAP") ) ) fsm.act("GAP", - counter.ce.eq(1), + counter_ce.eq(1), sink.ack.eq(int(ack_on_gap)), - If(counter.value == (gap-1), + If(counter == (gap-1), NextState("COPY") ) ) diff --git a/liteeth/core/mac/core/padding.py b/liteeth/core/mac/core/padding.py index 5962f76..3aa8939 100644 --- a/liteeth/core/mac/core/padding.py +++ b/liteeth/core/mac/core/padding.py @@ -10,19 +10,26 @@ class LiteEthMACPaddingInserter(Module): padding_limit = math.ceil(padding/(dw/8))-1 - self.submodules.counter = counter = Counter(16, reset=1) + counter = Signal(16, reset=1) counter_done = Signal() + counter_reset = Signal() + counter_ce = Signal() + self.sync += If(counter_reset, + counter.eq(1) + ).Elif(counter_ce, + counter.eq(counter + 1) + ) self.comb += [ - counter.reset.eq(sink.stb & sink.sop & sink.ack), - counter.ce.eq(source.stb & source.ack), - counter_done.eq(counter.value >= padding_limit), + counter_reset.eq(sink.stb & sink.sop & sink.ack), + counter_ce.eq(source.stb & source.ack), + counter_done.eq(counter >= padding_limit), ] self.submodules.fsm = fsm = FSM(reset_state="IDLE") fsm.act("IDLE", Record.connect(sink, source), If(source.stb & source.ack, - counter.ce.eq(1), + counter_ce.eq(1), If(sink.eop, If(~counter_done, source.eop.eq(0), diff --git a/liteeth/core/mac/frontend/sram.py b/liteeth/core/mac/frontend/sram.py index 6482359..9d85386 100644 --- a/liteeth/core/mac/frontend/sram.py +++ b/liteeth/core/mac/frontend/sram.py @@ -1,7 +1,8 @@ from liteeth.common import * -from migen.bank.description import * -from migen.bank.eventmanager import * +from litex.soc.interconnect.csr import * +from litex.soc.interconnect.csr_eventmanager import * + class LiteEthMACSRAMWriter(Module, AutoCSR): @@ -36,12 +37,19 @@ class LiteEthMACSRAMWriter(Module, AutoCSR): ).Else( increment.eq(4) ) - counter = Counter(lengthbits, increment=increment) - self.submodules += counter + counter = Signal(lengthbits) + counter_reset = Signal() + counter_ce = Signal() + self.sync += If(counter_reset, + counter.eq(0) + ).Elif(counter_ce, + counter.eq(counter + increment) + ) # slot computation - slot = Counter(slotbits) - self.submodules += slot + slot = Signal(slotbits) + slot_ce = Signal() + self.sync += If(slot_ce, slot.eq(slot + 1)) ongoing = Signal() @@ -57,13 +65,13 @@ class LiteEthMACSRAMWriter(Module, AutoCSR): If(sink.stb & sink.sop, If(fifo.sink.ack, ongoing.eq(1), - counter.ce.eq(1), + counter_ce.eq(1), NextState("WRITE") ) ) ) fsm.act("WRITE", - counter.ce.eq(sink.stb), + counter_ce.eq(sink.stb), ongoing.eq(1), If(sink.stb & sink.eop, If((sink.error & sink.last_be) != 0, @@ -74,16 +82,16 @@ class LiteEthMACSRAMWriter(Module, AutoCSR): ) ) fsm.act("DISCARD", - counter.reset.eq(1), + counter_reset.eq(1), NextState("IDLE") ) self.comb += [ - fifo.sink.slot.eq(slot.value), - fifo.sink.length.eq(counter.value) + fifo.sink.slot.eq(slot), + fifo.sink.length.eq(counter) ] fsm.act("TERMINATE", - counter.reset.eq(1), - slot.ce.eq(1), + counter_reset.eq(1), + slot_ce.eq(1), fifo.sink.stb.eq(1), NextState("IDLE") ) @@ -106,13 +114,13 @@ class LiteEthMACSRAMWriter(Module, AutoCSR): cases = {} for n, port in enumerate(ports): cases[n] = [ - ports[n].adr.eq(counter.value[2:]), + ports[n].adr.eq(counter[2:]), ports[n].dat_w.eq(sink.data), If(sink.stb & ongoing, ports[n].we.eq(0xf) ) ] - self.comb += Case(slot.value, cases) + self.comb += Case(slot, cases) class LiteEthMACSRAMReader(Module, AutoCSR): @@ -145,7 +153,15 @@ class LiteEthMACSRAMReader(Module, AutoCSR): ] # length computation - self.submodules.counter = counter = Counter(lengthbits, increment=4) + counter = Signal(lengthbits) + counter_reset = Signal() + counter_ce = Signal() + self.sync += If(counter_reset, + counter.eq(0) + ).Elif(counter_ce, + counter.eq(counter + 4) + ) + # fsm first = Signal() @@ -156,7 +172,7 @@ class LiteEthMACSRAMReader(Module, AutoCSR): self.submodules += fsm fsm.act("IDLE", - counter.reset.eq(1), + counter_reset.eq(1), If(fifo.source.stb, NextState("CHECK") ) @@ -187,7 +203,7 @@ class LiteEthMACSRAMReader(Module, AutoCSR): source.sop.eq(first), source.eop.eq(last), If(source.ack, - counter.ce.eq(~last), + counter_ce.eq(~last), NextState("CHECK") ) ) @@ -205,7 +221,7 @@ class LiteEthMACSRAMReader(Module, AutoCSR): first.eq(0) ) ] - self.comb += last.eq((counter.value + 4) >= fifo.source.length) + self.comb += last.eq((counter + 4) >= fifo.source.length) self.sync += last_d.eq(last) # memory @@ -221,7 +237,7 @@ class LiteEthMACSRAMReader(Module, AutoCSR): cases = {} for n, port in enumerate(ports): - self.comb += ports[n].adr.eq(counter.value[2:]) + self.comb += ports[n].adr.eq(counter[2:]) cases[n] = [source.data.eq(port.dat_r)] self.comb += Case(rd_slot, cases) diff --git a/liteeth/core/mac/frontend/wishbone.py b/liteeth/core/mac/frontend/wishbone.py index d39a671..3c0e093 100644 --- a/liteeth/core/mac/frontend/wishbone.py +++ b/liteeth/core/mac/frontend/wishbone.py @@ -1,7 +1,7 @@ from liteeth.common import * -from liteeth.core.mac.frontend import sram +from litex.soc.cores.liteeth_mini.mac.frontend import sram -from migen.bus import wishbone +from litex.soc.interconnect import wishbone from migen.fhdl.simplify import FullMemoryWE diff --git a/liteeth/frontend/etherbone.py b/liteeth/frontend/etherbone.py index 711a10f..d3dbca5 100644 --- a/liteeth/frontend/etherbone.py +++ b/liteeth/frontend/etherbone.py @@ -1,5 +1,6 @@ from liteeth.common import * -from migen.bus import wishbone + +from litex.soc.interconnect import wishbone # etherbone packet diff --git a/liteeth/phy/__init__.py b/liteeth/phy/__init__.py index 1f732c1..ce02482 100644 --- a/liteeth/phy/__init__.py +++ b/liteeth/phy/__init__.py @@ -7,7 +7,7 @@ def LiteEthPHY(clock_pads, pads, clk_freq=None, **kwargs): # This is a simulation PHY from liteeth.phy.sim import LiteEthPHYSim return LiteEthPHYSim(pads) - elif hasattr(clock_pads, "gtx") and flen(pads.tx_data) == 8: + elif hasattr(clock_pads, "gtx") and len(pads.tx_data) == 8: if hasattr(clock_pads, "tx"): # This is a 10/100/1G PHY from liteeth.phy.gmii_mii import LiteEthPHYGMIIMII @@ -19,7 +19,7 @@ def LiteEthPHY(clock_pads, pads, clk_freq=None, **kwargs): elif hasattr(pads, "rx_ctl"): # This is a 10/100/1G RGMII PHY raise ValueError("RGMII PHYs are specific to vendors (for now), use direct instantiation") - elif flen(pads.tx_data) == 4: + elif len(pads.tx_data) == 4: # This is a MII PHY from liteeth.phy.mii import LiteEthPHYMII return LiteEthPHYMII(clock_pads, pads, **kwargs) diff --git a/liteeth/phy/gmii.py b/liteeth/phy/gmii.py index e5a8efe..8a6aa94 100644 --- a/liteeth/phy/gmii.py +++ b/liteeth/phy/gmii.py @@ -72,11 +72,13 @@ class LiteEthPHYGMIICRG(Module, AutoCSR): if with_hw_init_reset: reset = Signal() + counter = Signal(max=512) counter_done = Signal() - self.submodules.counter = counter = Counter(max=512) + counter_ce = Signal() + self.sync += If(counter_ce, counter.eq(counter + 1)) self.comb += [ - counter_done.eq(counter.value == 256), - counter.ce.eq(~counter_done), + counter_done.eq(counter == 256), + counter_ce.eq(~counter_done), reset.eq(~counter_done | self._reset.storage) ] else: @@ -92,6 +94,6 @@ class LiteEthPHYGMII(Module, AutoCSR): def __init__(self, clock_pads, pads, with_hw_init_reset=True): self.dw = 8 self.submodules.crg = LiteEthPHYGMIICRG(clock_pads, pads, with_hw_init_reset) - self.submodules.tx = RenameClockDomains(LiteEthPHYGMIITX(pads), "eth_tx") - self.submodules.rx = RenameClockDomains(LiteEthPHYGMIIRX(pads), "eth_rx") + self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYGMIITX(pads)) + self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYGMIIRX(pads)) self.sink, self.source = self.tx.sink, self.rx.source diff --git a/liteeth/phy/gmii_mii.py b/liteeth/phy/gmii_mii.py index 5a17b5c..607b247 100644 --- a/liteeth/phy/gmii_mii.py +++ b/liteeth/phy/gmii_mii.py @@ -1,9 +1,9 @@ from migen.genlib.io import DDROutput -from migen.flow.plumbing import Multiplexer, Demultiplexer from migen.genlib.cdc import PulseSynchronizer -from liteeth.common import * +from litex.soc.interconnect.stream import Multiplexer, Demultiplexer +from liteeth.common import * from liteeth.phy.gmii import LiteEthPHYGMIICRG from liteeth.phy.mii import LiteEthPHYMIITX, LiteEthPHYMIIRX from liteeth.phy.gmii import LiteEthPHYGMIITX, LiteEthPHYGMIIRX @@ -118,20 +118,28 @@ class LiteEthGMIIMIIModeDetection(Module, AutoCSR): self.submodules += eth_ps # sys_clk domain counter - sys_counter = Counter(24) - self.submodules += sys_counter + sys_counter = Signal(24) + sys_counter_reset = Signal() + sys_counter_ce = Signal() + self.sync += [ + If(sys_counter_reset, + sys_counter.eq(0) + ).Elif(sys_counter_ce, + sys_counter.eq(sys_counter + 1) + ) + ] fsm = FSM(reset_state="IDLE") self.submodules += fsm fsm.act("IDLE", - sys_counter.reset.eq(1), + sys_counter_reset.eq(1), If(sys_tick, NextState("COUNT") ) ) fsm.act("COUNT", - sys_counter.ce.eq(1), + sys_counter_ce.eq(1), If(sys_tick, NextState("DETECTION") ) @@ -139,7 +147,7 @@ class LiteEthGMIIMIIModeDetection(Module, AutoCSR): fsm.act("DETECTION", update_mode.eq(1), # if freq < 125MHz-5% use MII mode - If(sys_counter.value > int((clk_freq/125000000)*1024*1.05), + If(sys_counter > int((clk_freq/125000000)*1024*1.05), mode.eq(1) # if freq >= 125MHz-5% use GMII mode ).Else( @@ -156,6 +164,6 @@ class LiteEthPHYGMIIMII(Module, AutoCSR): self.submodules.mode_detection = LiteEthGMIIMIIModeDetection(clk_freq) mode = self.mode_detection.mode self.submodules.crg = LiteEthPHYGMIICRG(clock_pads, pads, with_hw_init_reset, mode == modes["MII"]) - self.submodules.tx = RenameClockDomains(LiteEthPHYGMIIMIITX(pads, mode), "eth_tx") - self.submodules.rx = RenameClockDomains(LiteEthPHYGMIIMIIRX(pads, mode), "eth_rx") + self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYGMIIMIITX(pads, mode)) + self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYGMIIMIIRX(pads, mode)) self.sink, self.source = self.tx.sink, self.rx.source diff --git a/liteeth/phy/mii.py b/liteeth/phy/mii.py index fccc53d..8363623 100644 --- a/liteeth/phy/mii.py +++ b/liteeth/phy/mii.py @@ -46,7 +46,7 @@ class LiteEthPHYMIIRX(Module): converter = Converter(converter_description(4), converter_description(8)) - converter = InsertReset(converter) + converter = ResetInserter()(converter) self.submodules += converter self.sync += [ @@ -101,6 +101,6 @@ class LiteEthPHYMII(Module, AutoCSR): def __init__(self, clock_pads, pads, with_hw_init_reset=True): self.dw = 8 self.submodules.crg = LiteEthPHYMIICRG(clock_pads, pads, with_hw_init_reset) - self.submodules.tx = RenameClockDomains(LiteEthPHYMIITX(pads), "eth_tx") - self.submodules.rx = RenameClockDomains(LiteEthPHYMIIRX(pads), "eth_rx") + self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYMIITX(pads)) + self.submodules.rx = ClockDomainsRenamer("eth_tx")(LiteEthPHYMIIRX(pads)) self.sink, self.source = self.tx.sink, self.rx.source