diff --git a/liteeth/gen.py b/liteeth/gen.py
index 9b62b75..df467f9 100755
--- a/liteeth/gen.py
+++ b/liteeth/gen.py
@@ -219,12 +219,13 @@ class MACCore(PHYCore):
 
         # MAC --------------------------------------------------------------------------------------
         self.submodules.ethmac = LiteEthMAC(
-            phy        = self.ethphy,
-            dw         = 32,
-            interface  = "wishbone",
-            endianness = core_config["endianness"],
-            nrxslots   = nrxslots,
-            ntxslots   = ntxslots)
+            phy            = self.ethphy,
+            dw             = 32,
+            interface      = "wishbone",
+            endianness     = core_config["endianness"],
+            nrxslots       = nrxslots,
+            ntxslots       = ntxslots,
+            full_memory_we = core_config.get("full_memory_we", False))
         self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus)
         self.add_memory_region("ethmac", self.mem_map["ethmac"], mac_memsize, type="io")
         self.add_csr("ethmac")
diff --git a/liteeth/mac/__init__.py b/liteeth/mac/__init__.py
index 42cc993..7dd33c9 100644
--- a/liteeth/mac/__init__.py
+++ b/liteeth/mac/__init__.py
@@ -19,7 +19,8 @@ class LiteEthMAC(Module, AutoCSR):
         nrxslots          = 2,
         ntxslots          = 2,
         hw_mac            = None,
-        timestamp         = None):
+        timestamp         = None,
+        full_memory_we    = False):
         assert interface in ["crossbar", "wishbone", "hybrid"]
         self.submodules.core = LiteEthMACCore(phy, dw, endianness, with_preamble_crc)
         self.csrs = []
@@ -38,13 +39,23 @@ class LiteEthMAC(Module, AutoCSR):
             self.rx_slots  = CSRConstant(nrxslots)
             self.tx_slots  = CSRConstant(ntxslots)
             self.slot_size = CSRConstant(2**bits_for(eth_mtu))
-            self.submodules.interface = FullMemoryWE()(LiteEthMACWishboneInterface(
+            wishbone_interface = LiteEthMACWishboneInterface(
                 dw         = 32,
                 nrxslots   = nrxslots,
                 ntxslots   = ntxslots,
                 endianness = endianness,
                 timestamp  = timestamp,
-            ))
+            )
+            # On some targets (Intel/Altera), the complex ports aren't inferred
+            # as block ram, but are created with LUTs.  FullMemoryWe splits such
+            # `Memory` instances up into 4 separate memory blocks, each
+            # containing 8 bits which gets inferred correctly on intel/altera.
+            # Yosys on ECP5 inferrs the original correctly, so FullMemoryWE
+            # leads to additional block ram instances being used, which
+            # increases memory usage by a lot.
+            if full_memory_we:
+                wishbone_interface = FullMemoryWE()(wishbone_interface)
+            self.submodules.interface = wishbone_interface
             self.ev, self.bus = self.interface.sram.ev, self.interface.bus
             self.csrs = self.interface.get_csrs() + self.core.get_csrs()
             if interface == "hybrid":