phy/s6rgmii: fix missing last signal

2016-03-29 16:53:37 +02:00 · 2016-03-29 16:53:37 +02:00 · a189b2c195
parent b394f2f45e
commit a189b2c195
1 changed files with 2 additions and 0 deletions
--- a/liteeth/phy/s6rgmii.py
+++ b/liteeth/phy/s6rgmii.py
@ -59,6 +59,8 @@ class LiteEthPHYRGMIIRX(Module):
        rx_ctl_d = Signal()
        self.sync += rx_ctl_d.eq(rx_ctl)

+        last = Signal()
+        self.comb += last.eq(~rx_ctl & rx_ctl_d)
        self.sync += [
            source.valid.eq(rx_ctl),
            source.data.eq(rx_data)