Hardware
/
liteeth
mirror of https://github.com/enjoy-digital/liteeth.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

phy/efinix: Use new LiteX's ClkInput/Output abstraction to simplify code/avoid duplications.

This commit is contained in:
Florent Kermarrec 2023-09-12 09:34:43 +02:00
parent 618f20b603
commit a6775fe1af
2 changed files with 18 additions and 44 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

31
liteeth/phy/titaniumrgmii.py
View File

@ -12,7 +12,7 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
from litex.gen import * from litex.gen import *
from litex.build.io import DDROutput, DDRInput from litex.build.io import ClkInput, ClkOutput, DDROutput, DDRInput
from litex.build.generic_platform import * from litex.build.generic_platform import *
from litex.soc.cores.clock import * from litex.soc.cores.clock import *
@ -128,30 +128,17 @@ class LiteEthPHYRGMIICRG(LiteXModule):
# RX Clk. # RX Clk.
# ------- # -------
eth_rx_clk = platform.add_iface_io(f"auto_eth{n}_rx_clk_in") self.specials += ClkInput(
block = { i = clock_pads.rx,
"type" : "GPIO", o = f"auto_eth{n}_rx_clk_in", # FIXME: Use Clk Signal.
"size" : 1, )
"location" : platform.get_pin_location(clock_pads.rx)[0],
"properties" : platform.get_pin_properties(clock_pads.rx),
"name" : platform.get_pin_name(eth_rx_clk),
"mode" : "INPUT_CLK"
}
platform.toolchain.ifacewriter.blocks.append(block)
platform.toolchain.excluded_ios.append(clock_pads.rx)
# TX Clk. # TX Clk.
# ------- # -------
block = { self.specials += ClkOutput(
"type" : "GPIO", i = f"auto_eth{n}_tx_clk_delayed", # FIXME: Use Clk Signal.
"size" : 1, o = clock_pads.tx
"location" : platform.get_pin_location(clock_pads.tx)[0], )
"properties" : platform.get_pin_properties(clock_pads.tx),
"name" : f"auto_eth{n}_tx_clk_delayed",
"mode" : "OUTPUT_CLK"
}
platform.toolchain.ifacewriter.blocks.append(block)
platform.toolchain.excluded_ios.append(clock_pads.tx)
# TX PLL. # TX PLL.
# ------- # -------

31
liteeth/phy/trionrgmii.py
View File

@ -12,7 +12,7 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
from litex.gen import * from litex.gen import *
from litex.build.io import DDROutput, DDRInput from litex.build.io import ClkInput, ClkOutput, DDROutput, DDRInput
from litex.build.generic_platform import * from litex.build.generic_platform import *
from litex.soc.cores.clock import * from litex.soc.cores.clock import *
@ -128,30 +128,17 @@ class LiteEthPHYRGMIICRG(LiteXModule):
# RX Clk. # RX Clk.
# ------- # -------
eth_rx_clk = platform.add_iface_io(f"auto_eth{n}_rx_clk_in") self.specials += ClkInput(
block = { i = clock_pads.rx,
"type" : "GPIO", o = f"auto_eth{n}_rx_clk_in", # FIXME: Use Clk Signal.
"size" : 1, )
"location" : platform.get_pin_location(clock_pads.rx)[0],
"properties" : platform.get_pin_properties(clock_pads.rx),
"name" : platform.get_pin_name(eth_rx_clk),
"mode" : "INPUT_CLK"
}
platform.toolchain.ifacewriter.blocks.append(block)
platform.toolchain.excluded_ios.append(clock_pads.rx)
# TX Clk. # TX Clk.
# ------- # -------
block = { self.specials += ClkOutput(
"type" : "GPIO", i = f"auto_eth{n}_tx_clk_delayed", # FIXME: Use Clk Signal.
"size" : 1, o = clock_pads.tx
"location" : platform.get_pin_location(clock_pads.tx)[0], )
"properties" : platform.get_pin_properties(clock_pads.tx),
"name" : f"auto_eth{n}_tx_clk_delayed",
"mode" : "OUTPUT_CLK"
}
platform.toolchain.ifacewriter.blocks.append(block)
platform.toolchain.excluded_ios.append(clock_pads.tx)
# TX PLL. # TX PLL.
# ------- # -------