From a696ccddb4dcf5635955d8456a67bc9d1fcf6ff5 Mon Sep 17 00:00:00 2001
From: Xiretza <xiretza@xiretza.xyz>
Date: Mon, 10 Feb 2020 11:01:31 +0100
Subject: [PATCH] Expose interrupt pin for standalone design

---
 liteeth/gen.py | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/liteeth/gen.py b/liteeth/gen.py
index 9c604e9..ac9621f 100644
--- a/liteeth/gen.py
+++ b/liteeth/gen.py
@@ -46,6 +46,8 @@ _io = [
     ("sys_clock", 0, Pins(1)),
     ("sys_reset", 1, Pins(1)),
 
+    ("interrupt", 0, Pins(1)),
+
     # MII PHY Pads
     ("mii_eth_clocks", 0,
         Subsignal("tx", Pins(1)),
@@ -223,6 +225,8 @@ class MACCore(PHYCore):
         self.submodules += bridge
         self.add_wb_master(bridge.wishbone)
 
+        self.comb += self.platform.request("interrupt").eq(self.ethmac.ev.irq)
+
 # UDP Core -----------------------------------------------------------------------------------------
 
 class UDPCore(PHYCore):