phy/pcs_1000basex: Minor changes/cleanups.
- Switch to LiteXModule. - Cosmetic cleanups for similarity with others modules. - Use K/D definition from litex.soc.cores.code_8b10b.
This commit is contained in:
Florent Kermarrec
parent
7046987ff1
commit
a9e41ef59b
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@ -11,33 +11,24 @@ from migen.genlib.fsm import *
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from migen.genlib.misc import WaitTimer
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from migen.genlib.cdc import PulseSynchronizer, BusSynchronizer
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from litex.gen import *
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from litex.soc.interconnect import stream
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from litex.soc.cores import code_8b10b
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from litex.soc.cores.code_8b10b import K, D, Encoder, Decoder
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from liteeth.common import *
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# PCS TX -------------------------------------------------------------------------------------------
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__all__ = ["TransmitPath", "ReceivePath", "PCS"]
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def K(x, y):
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return (y << 5) | x
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def D(x, y):
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return (y << 5) | x
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class TransmitPath(Module):
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class PCSTX(LiteXModule):
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def __init__(self, lsb_first=False):
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self.config_stb = Signal()
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self.config_reg = Signal(16)
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self.tx_stb = Signal()
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self.tx_ack = Signal()
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self.tx_data = Signal(8)
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self.tx_stb = Signal()
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self.tx_ack = Signal()
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self.tx_data = Signal(8)
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self.submodules.encoder = code_8b10b.Encoder(lsb_first=lsb_first)
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self.encoder = Encoder(lsb_first=lsb_first)
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# SGMII Speed Adaptation
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self.sgmii_speed = Signal(2)
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@ -48,12 +39,12 @@ class TransmitPath(Module):
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c_type = Signal()
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self.sync += parity.eq(~parity)
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config_reg_buffer = Signal(16)
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config_reg_buffer = Signal(16)
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load_config_reg_buffer = Signal()
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self.sync += If(load_config_reg_buffer, config_reg_buffer.eq(self.config_reg))
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# Timer for SGMII data rates
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timer = Signal(max=1000)
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# Timer for SGMII data rates.
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timer = Signal(max=1000)
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timer_en = Signal()
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self.sync += [
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If(~timer_en | (timer == 0),
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@ -69,26 +60,24 @@ class TransmitPath(Module):
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)
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]
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fsm = FSM()
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self.submodules += fsm
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self.fsm = fsm = FSM()
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fsm.act("START",
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If(self.config_stb,
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self.tx_ack.eq(1), # discard TX data if we are in config_reg phase
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self.tx_ack.eq(1), # Discard TX data if we are in config_reg phase.
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load_config_reg_buffer.eq(1),
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self.encoder.k[0].eq(1),
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self.encoder.d[0].eq(K(28, 5)),
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NextState("CONFIG_D")
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).Else(
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If(self.tx_stb,
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# the first byte sent is replaced by /S/
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# The first byte sent is replaced by /S/.
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self.tx_ack.eq((timer == 0)),
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timer_en.eq(1),
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self.encoder.k[0].eq(1),
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self.encoder.d[0].eq(K(27, 7)),
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NextState("DATA")
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).Else(
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self.tx_ack.eq(1), # discard TX data
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self.tx_ack.eq(1), # Discard TX data.
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self.encoder.k[0].eq(1),
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self.encoder.d[0].eq(K(28, 5)),
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NextState("IDLE")
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@ -113,13 +102,13 @@ class TransmitPath(Module):
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NextState("START")
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)
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fsm.act("IDLE",
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# due to latency in the encoder, we read here the disparity
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# Due to latency in the encoder, we read here the disparity
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# just before the K28.5 was sent. K28.5 flips the disparity.
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If(self.encoder.disparity[0],
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# correcting /I1/ (D5.6 preserves the disparity)
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# Correcting /I1/ (D5.6 preserves the disparity).
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self.encoder.d[0].eq(D(5, 6))
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).Else(
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# preserving /I2/ (D16.2 flips the disparity)
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# Preserving /I2/ (D16.2 flips the disparity).
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self.encoder.d[0].eq(D(16, 2))
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),
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NextState("START")
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@ -154,25 +143,26 @@ class TransmitPath(Module):
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NextState("START")
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)
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# PCS RX -------------------------------------------------------------------------------------------
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class ReceivePath(Module):
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class PCSRX(LiteXModule):
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def __init__(self, lsb_first=False):
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self.rx_en = Signal()
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self.rx_en = Signal()
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self.rx_data = Signal(8)
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self.seen_valid_ci = Signal()
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self.seen_valid_ci = Signal()
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self.seen_config_reg = Signal()
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self.config_reg = Signal(16)
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self.config_reg = Signal(16)
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self.submodules.decoder = code_8b10b.Decoder(lsb_first=lsb_first)
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self.decoder = Decoder(lsb_first=lsb_first)
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# SGMII Speed Adaptation
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# SGMII Speed Adaptation.
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self.sgmii_speed = Signal(2)
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self.sample_en = Signal()
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self.sample_en = Signal()
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# # #
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config_reg_lsb = Signal(8)
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config_reg_lsb = Signal(8)
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load_config_reg_lsb = Signal()
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load_config_reg_msb = Signal()
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self.sync += [
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@ -189,8 +179,8 @@ class ReceivePath(Module):
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first_preamble_byte = Signal()
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self.comb += self.rx_data.eq(Mux(first_preamble_byte, 0x55, self.decoder.d))
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# Timer for SGMII data rates
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timer = Signal(max=1000)
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# Timer for SGMII data rates.
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timer = Signal(max=1000)
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timer_en = Signal()
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self.sync += [
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If(~timer_en | (timer == 0),
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@ -209,9 +199,7 @@ class ReceivePath(Module):
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# Speed adaptation
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self.comb += self.sample_en.eq(self.rx_en & (timer == 0))
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fsm = FSM()
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self.submodules += fsm
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self.fsm = fsm = FSM()
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fsm.act("START",
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If(self.decoder.k,
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If(self.decoder.d == K(28, 5),
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@ -269,28 +257,26 @@ class ReceivePath(Module):
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)
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)
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# PCS ----------------------------------------------------------------------------------------------
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class PCS(Module):
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class PCS(LiteXModule):
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def __init__(self, lsb_first=False, check_period=6e-3, more_ack_time=10e-3):
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self.submodules.tx = ClockDomainsRenamer("eth_tx")(
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TransmitPath(lsb_first=lsb_first))
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self.submodules.rx = ClockDomainsRenamer("eth_rx")(
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ReceivePath(lsb_first=lsb_first))
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self.tx = ClockDomainsRenamer("eth_tx")(PCSTX(lsb_first=lsb_first))
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self.rx = ClockDomainsRenamer("eth_rx")(PCSRX(lsb_first=lsb_first))
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self.tbi_tx = self.tx.encoder.output[0]
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self.tbi_rx = self.rx.decoder.input
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self.sink = stream.Endpoint(eth_phy_description(8))
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self.sink = stream.Endpoint(eth_phy_description(8))
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self.source = stream.Endpoint(eth_phy_description(8))
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self.link_up = Signal()
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self.restart = Signal()
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self.lp_abi = BusSynchronizer(16, "eth_rx", "eth_tx")
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self.submodules += self.lp_abi
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# # #
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# endpoint interface
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# Endpoint interface.
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self.comb += [
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self.tx.tx_stb.eq(self.sink.valid),
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self.sink.ready.eq(self.tx.tx_ack),
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@ -301,11 +287,11 @@ class PCS(Module):
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self.sync.eth_rx += [
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rx_en_d.eq(self.rx.rx_en),
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self.source.valid.eq(self.rx.sample_en),
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self.source.data.eq(self.rx.rx_data)
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self.source.data.eq(self.rx.rx_data),
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]
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self.comb += self.source.last.eq(~self.rx.rx_en & rx_en_d)
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# main module
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# Main module.
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seen_valid_ci = PulseSynchronizer("eth_rx", "eth_tx")
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self.submodules += seen_valid_ci
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self.comb += seen_valid_ci.i.eq(self.rx.seen_valid_ci)
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@ -326,16 +312,16 @@ class PCS(Module):
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If(checker_tick, checker_ok.eq(0))
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]
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# Control if tx_config_reg should be empty
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# Control if tx_config_reg should be empty.
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tx_config_empty = Signal()
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# Detections in SGMII mode
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# Detections in SGMII mode.
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is_sgmii = Signal()
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linkdown = Signal()
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self.comb += [
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is_sgmii.eq(self.lp_abi.o[0]),
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# Detect that link is down:
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# - 1000BASE-X: linkup can be inferred by non-empty reg
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# - SGMII: linkup is indicated with bit 15
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# - 1000BASE-X : linkup can be inferred by non-empty reg.
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# - SGMII : linkup is indicated with bit 15.
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linkdown.eq((self.lp_abi.o[0] & ~self.lp_abi.o[15]) | (self.lp_abi.o == 0)),
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self.tx.sgmii_speed.eq(Mux(self.lp_abi.o[0],
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self.lp_abi.o[10:12], 0b10)),
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@ -345,32 +331,26 @@ class PCS(Module):
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autoneg_ack = Signal()
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self.comb += [
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self.tx.config_reg.eq(Mux(tx_config_empty, 0,
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(is_sgmii) | # SGMII: SGMII in-use
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(~is_sgmii << 5) | # 1000BASE-X: Full-duplex
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(Mux(self.lp_abi.o[0], # SGMII: Speed
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(is_sgmii) | # SGMII: SGMII in-use
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(~is_sgmii << 5) | # 1000BASE-X: Full-duplex
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(Mux(self.lp_abi.o[0], # SGMII: Speed
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self.lp_abi.o[10:12], 0) << 10) |
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(is_sgmii << 12) | # SGMII: Full-duplex
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(autoneg_ack << 14) | # SGMII/1000BASE-X: Acknowledge Bit
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(is_sgmii & self.link_up) # SGMII: Link-up
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(is_sgmii << 12) | # SGMII: Full-duplex
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(autoneg_ack << 14) | # SGMII/1000BASE-X: Acknowledge Bit
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(is_sgmii & self.link_up) # SGMII: Link-up
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))
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]
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rx_config_reg_abi = PulseSynchronizer("eth_rx", "eth_tx")
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rx_config_reg_ack = PulseSynchronizer("eth_rx", "eth_tx")
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self.submodules += [
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rx_config_reg_abi, rx_config_reg_ack
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]
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self.submodules += rx_config_reg_abi, rx_config_reg_ack
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more_ack_timer = ClockDomainsRenamer("eth_tx")(
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WaitTimer(ceil(more_ack_time*125e6)))
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more_ack_timer = ClockDomainsRenamer("eth_tx")(WaitTimer(ceil(more_ack_time*125e6)))
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# SGMII: use 1.6ms link_timer
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sgmii_ack_timer = ClockDomainsRenamer("eth_tx")(
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WaitTimer(ceil(1.6e-3*125e6)))
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sgmii_ack_timer = ClockDomainsRenamer("eth_tx")(WaitTimer(ceil(1.6e-3*125e6)))
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self.submodules += more_ack_timer, sgmii_ack_timer
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fsm = ClockDomainsRenamer("eth_tx")(FSM())
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self.submodules += fsm
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self.fsm = fsm = ClockDomainsRenamer("eth_tx")(FSM())
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# AN_ENABLE
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fsm.act("AUTONEG_BREAKLINK",
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self.tx.config_stb.eq(1),
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@ -427,7 +407,7 @@ class PCS(Module):
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)
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)
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c_counter = Signal(max=5)
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c_counter = Signal(max=5)
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prev_config_reg = Signal(16)
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self.sync.eth_rx += [
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# Restart consistency counter
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