diff --git a/liteeth/phy/a7_1000basex.py b/liteeth/phy/a7_1000basex.py
index 8ccb0c6..44822be 100644
--- a/liteeth/phy/a7_1000basex.py
+++ b/liteeth/phy/a7_1000basex.py
@@ -26,8 +26,7 @@ class A7_1000BASEX(LiteXModule):
     rx_clk_freq = 125e6
     tx_clk_freq = 125e6
     def __init__(self, qpll_channel, data_pads, sys_clk_freq, with_csr=True, rx_polarity=0, tx_polarity=0):
-        pcs = PCS(lsb_first=True)
-        self.submodules += pcs
+        self.pcs = pcs = PCS(lsb_first=True)
 
         self.sink    = pcs.sink
         self.source  = pcs.source
@@ -720,8 +719,7 @@ class A7_1000BASEX(LiteXModule):
         self.comb += rx_mmcm_locked.eq(rx_mmcm.locked)
 
         # Transceiver init
-        tx_init = GTPTxInit(sys_clk_freq)
-        self.submodules += tx_init
+        self.tx_init = tx_init = GTPTxInit(sys_clk_freq)
         self.comb += [
             qpll_channel.reset.eq(tx_init.qpll_reset),
             tx_init.qpll_lock.eq(qpll_channel.lock),
@@ -730,8 +728,7 @@ class A7_1000BASEX(LiteXModule):
         self.sync += tx_mmcm_reset.eq(~qpll_channel.lock)
         tx_mmcm_reset.attr.add("no_retiming")
 
-        rx_init = GTPRxInit(sys_clk_freq)
-        self.submodules += rx_init
+        self.rx_init = rx_init = GTPRxInit(sys_clk_freq)
         self.comb += [
             rx_init.enable.eq(tx_init.done),
             rx_reset.eq(rx_init.rx_reset | self.reset),
diff --git a/liteeth/phy/k7_1000basex.py b/liteeth/phy/k7_1000basex.py
index 8ac4852..33956cf 100644
--- a/liteeth/phy/k7_1000basex.py
+++ b/liteeth/phy/k7_1000basex.py
@@ -27,8 +27,7 @@ class K7_1000BASEX(LiteXModule):
     tx_clk_freq = 125e6
     def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq, refclk_freq=200e6, with_csr=True, rx_polarity=0, tx_polarity=0):
         assert refclk_freq in [200e6]
-        pcs = PCS(lsb_first=True)
-        self.submodules += pcs
+        self.pcs = pcs = PCS(lsb_first=True)
 
         self.sink    = pcs.sink
         self.source  = pcs.source
@@ -740,8 +739,7 @@ class K7_1000BASEX(LiteXModule):
         self.comb += rx_mmcm_locked.eq(rx_mmcm.locked)
 
         # Transceiver init
-        tx_init = ResetInserter()(GTXTXInit(sys_clk_freq, buffer_enable=True))
-        self.submodules += tx_init
+        self.tx_init = tx_init = ResetInserter()(GTXTXInit(sys_clk_freq, buffer_enable=True))
         self.comb += [
             tx_init.reset.eq(self.reset),
             pll.reset.eq(tx_init.pllreset),
@@ -752,9 +750,7 @@ class K7_1000BASEX(LiteXModule):
         self.sync += tx_mmcm_reset.eq(~pll.lock)
         tx_mmcm_reset.attr.add("no_retiming")
 
-
-        rx_init = ResetInserter()(GTXRXInit(sys_clk_freq, buffer_enable=True))
-        self.submodules += rx_init
+        self.rx_init = rx_init = ResetInserter()(GTXRXInit(sys_clk_freq, buffer_enable=True))
         self.comb += [
             rx_init.reset.eq(~tx_init.done | self.reset),
             rx_init.plllock.eq(pll.lock),
diff --git a/liteeth/phy/ku_1000basex.py b/liteeth/phy/ku_1000basex.py
index e5034bb..080d16c 100644
--- a/liteeth/phy/ku_1000basex.py
+++ b/liteeth/phy/ku_1000basex.py
@@ -26,8 +26,7 @@ class KU_1000BASEX(LiteXModule):
     tx_clk_freq = 125e6
     def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq, refclk_freq=200e6, with_csr=True, rx_polarity=0, tx_polarity=0):
         assert refclk_freq in [200e6, 156.25e6]
-        pcs = PCS(lsb_first=True)
-        self.submodules += pcs
+        self.pcs = pcs = PCS(lsb_first=True)
 
         self.sink    = pcs.sink
         self.source  = pcs.source
diff --git a/liteeth/phy/usp_gth_1000basex.py b/liteeth/phy/usp_gth_1000basex.py
index 6b51daf..68160f6 100644
--- a/liteeth/phy/usp_gth_1000basex.py
+++ b/liteeth/phy/usp_gth_1000basex.py
@@ -26,8 +26,7 @@ class USP_GTH_1000BASEX(LiteXModule):
     tx_clk_freq = 125e6
     def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq, refclk_freq=200e6, with_csr=True, rx_polarity=0, tx_polarity=0):
         assert refclk_freq in [200e6, 156.25e6]
-        pcs = PCS(lsb_first=True)
-        self.submodules += pcs
+        self.pcs = pcs = PCS(lsb_first=True)
 
         self.sink    = pcs.sink
         self.source  = pcs.source
diff --git a/liteeth/phy/usp_gty_1000basex.py b/liteeth/phy/usp_gty_1000basex.py
index 342df11..24e5476 100644
--- a/liteeth/phy/usp_gty_1000basex.py
+++ b/liteeth/phy/usp_gty_1000basex.py
@@ -26,8 +26,7 @@ class USP_GTY_1000BASEX(LiteXModule):
     tx_clk_freq = 125e6
     def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq, refclk_freq=200e6, with_csr=True, rx_polarity=0, tx_polarity=0):
         assert refclk_freq in [200e6, 156.25e6]
-        pcs = PCS(lsb_first=True)
-        self.submodules += pcs
+        self.pcs = pcs = PCS(lsb_first=True)
 
         self.sink    = pcs.sink
         self.source  = pcs.source