Hardware
/
liteeth
mirror of https://github.com/enjoy-digital/liteeth.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

phy/1000basex: Expose pcs, tx_init and rx_init modules to ease debug.

This commit is contained in:
Florent Kermarrec 2024-03-04 16:17:39 +01:00
parent 3061bf91ce
commit ab4606c5a1
5 changed files with 9 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
liteeth/phy/a7_1000basex.py
View File

@ -26,8 +26,7 @@ class A7_1000BASEX(LiteXModule):
rx_clk_freq = 125e6 rx_clk_freq = 125e6
tx_clk_freq = 125e6 tx_clk_freq = 125e6
def __init__(self, qpll_channel, data_pads, sys_clk_freq, with_csr=True, rx_polarity=0, tx_polarity=0): def __init__(self, qpll_channel, data_pads, sys_clk_freq, with_csr=True, rx_polarity=0, tx_polarity=0):
pcs = PCS(lsb_first=True) self.pcs = pcs = PCS(lsb_first=True)
self.submodules += pcs
self.sink = pcs.sink self.sink = pcs.sink
self.source = pcs.source self.source = pcs.source
@ -720,8 +719,7 @@ class A7_1000BASEX(LiteXModule):
self.comb += rx_mmcm_locked.eq(rx_mmcm.locked) self.comb += rx_mmcm_locked.eq(rx_mmcm.locked)
# Transceiver init # Transceiver init
tx_init = GTPTxInit(sys_clk_freq) self.tx_init = tx_init = GTPTxInit(sys_clk_freq)
self.submodules += tx_init
self.comb += [ self.comb += [
qpll_channel.reset.eq(tx_init.qpll_reset), qpll_channel.reset.eq(tx_init.qpll_reset),
tx_init.qpll_lock.eq(qpll_channel.lock), tx_init.qpll_lock.eq(qpll_channel.lock),
@ -730,8 +728,7 @@ class A7_1000BASEX(LiteXModule):
self.sync += tx_mmcm_reset.eq(~qpll_channel.lock) self.sync += tx_mmcm_reset.eq(~qpll_channel.lock)
tx_mmcm_reset.attr.add("no_retiming") tx_mmcm_reset.attr.add("no_retiming")
rx_init = GTPRxInit(sys_clk_freq) self.rx_init = rx_init = GTPRxInit(sys_clk_freq)
self.submodules += rx_init
self.comb += [ self.comb += [
rx_init.enable.eq(tx_init.done), rx_init.enable.eq(tx_init.done),
rx_reset.eq(rx_init.rx_reset | self.reset), rx_reset.eq(rx_init.rx_reset | self.reset),

10
liteeth/phy/k7_1000basex.py
View File

@ -27,8 +27,7 @@ class K7_1000BASEX(LiteXModule):
tx_clk_freq = 125e6 tx_clk_freq = 125e6
def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq, refclk_freq=200e6, with_csr=True, rx_polarity=0, tx_polarity=0): def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq, refclk_freq=200e6, with_csr=True, rx_polarity=0, tx_polarity=0):
assert refclk_freq in [200e6] assert refclk_freq in [200e6]
pcs = PCS(lsb_first=True) self.pcs = pcs = PCS(lsb_first=True)
self.submodules += pcs
self.sink = pcs.sink self.sink = pcs.sink
self.source = pcs.source self.source = pcs.source
@ -740,8 +739,7 @@ class K7_1000BASEX(LiteXModule):
self.comb += rx_mmcm_locked.eq(rx_mmcm.locked) self.comb += rx_mmcm_locked.eq(rx_mmcm.locked)
# Transceiver init # Transceiver init
tx_init = ResetInserter()(GTXTXInit(sys_clk_freq, buffer_enable=True)) self.tx_init = tx_init = ResetInserter()(GTXTXInit(sys_clk_freq, buffer_enable=True))
self.submodules += tx_init
self.comb += [ self.comb += [
tx_init.reset.eq(self.reset), tx_init.reset.eq(self.reset),
pll.reset.eq(tx_init.pllreset), pll.reset.eq(tx_init.pllreset),
@ -752,9 +750,7 @@ class K7_1000BASEX(LiteXModule):
self.sync += tx_mmcm_reset.eq(~pll.lock) self.sync += tx_mmcm_reset.eq(~pll.lock)
tx_mmcm_reset.attr.add("no_retiming") tx_mmcm_reset.attr.add("no_retiming")
self.rx_init = rx_init = ResetInserter()(GTXRXInit(sys_clk_freq, buffer_enable=True))
rx_init = ResetInserter()(GTXRXInit(sys_clk_freq, buffer_enable=True))
self.submodules += rx_init
self.comb += [ self.comb += [
rx_init.reset.eq(~tx_init.done | self.reset), rx_init.reset.eq(~tx_init.done | self.reset),
rx_init.plllock.eq(pll.lock), rx_init.plllock.eq(pll.lock),

3
liteeth/phy/ku_1000basex.py
View File

@ -26,8 +26,7 @@ class KU_1000BASEX(LiteXModule):
tx_clk_freq = 125e6 tx_clk_freq = 125e6
def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq, refclk_freq=200e6, with_csr=True, rx_polarity=0, tx_polarity=0): def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq, refclk_freq=200e6, with_csr=True, rx_polarity=0, tx_polarity=0):
assert refclk_freq in [200e6, 156.25e6] assert refclk_freq in [200e6, 156.25e6]
pcs = PCS(lsb_first=True) self.pcs = pcs = PCS(lsb_first=True)
self.submodules += pcs
self.sink = pcs.sink self.sink = pcs.sink
self.source = pcs.source self.source = pcs.source

3
liteeth/phy/usp_gth_1000basex.py
View File

@ -26,8 +26,7 @@ class USP_GTH_1000BASEX(LiteXModule):
tx_clk_freq = 125e6 tx_clk_freq = 125e6
def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq, refclk_freq=200e6, with_csr=True, rx_polarity=0, tx_polarity=0): def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq, refclk_freq=200e6, with_csr=True, rx_polarity=0, tx_polarity=0):
assert refclk_freq in [200e6, 156.25e6] assert refclk_freq in [200e6, 156.25e6]
pcs = PCS(lsb_first=True) self.pcs = pcs = PCS(lsb_first=True)
self.submodules += pcs
self.sink = pcs.sink self.sink = pcs.sink
self.source = pcs.source self.source = pcs.source

3
liteeth/phy/usp_gty_1000basex.py
View File

@ -26,8 +26,7 @@ class USP_GTY_1000BASEX(LiteXModule):
tx_clk_freq = 125e6 tx_clk_freq = 125e6
def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq, refclk_freq=200e6, with_csr=True, rx_polarity=0, tx_polarity=0): def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq, refclk_freq=200e6, with_csr=True, rx_polarity=0, tx_polarity=0):
assert refclk_freq in [200e6, 156.25e6] assert refclk_freq in [200e6, 156.25e6]
pcs = PCS(lsb_first=True) self.pcs = pcs = PCS(lsb_first=True)
self.submodules += pcs
self.sink = pcs.sink self.sink = pcs.sink
self.source = pcs.source self.source = pcs.source