diff --git a/liteeth/mac/__init__.py b/liteeth/mac/__init__.py
index e1edaa7..3f863ba 100644
--- a/liteeth/mac/__init__.py
+++ b/liteeth/mac/__init__.py
@@ -16,9 +16,8 @@ class LiteEthMAC(Module, AutoCSR):
         interface         = "crossbar",
         endianness        = "big",
         with_preamble_crc = True,
-        nrxslots          = 2,
-        ntxslots          = 2,
-        tx_write_only     = False,
+        nrxslots          = 2, rxslots_read_only  = True,
+        ntxslots          = 2, txslots_write_only = False,
         hw_mac            = None,
         timestamp         = None,
         full_memory_we    = False,
@@ -52,11 +51,10 @@ class LiteEthMAC(Module, AutoCSR):
             self.slot_size = CSRConstant(2**bits_for(eth_mtu))
             wishbone_interface = LiteEthMACWishboneInterface(
                 dw         = dw,
-                nrxslots   = nrxslots,
-                ntxslots   = ntxslots,
+                nrxslots   = nrxslots, rxslots_read_only  = rxslots_read_only,
+                ntxslots   = ntxslots, txslots_write_only = txslots_write_only,
                 endianness = endianness,
                 timestamp  = timestamp,
-                tx_write_only = tx_write_only,
             )
             # On some targets (Intel/Altera), the complex ports aren't inferred
             # as block ram, but are created with LUTs.  FullMemoryWe splits such
diff --git a/liteeth/mac/wishbone.py b/liteeth/mac/wishbone.py
index 702a7a1..1eeffbf 100644
--- a/liteeth/mac/wishbone.py
+++ b/liteeth/mac/wishbone.py
@@ -16,7 +16,10 @@ from litex.soc.interconnect import wishbone
 # MAC Wishbone Interface ---------------------------------------------------------------------------
 
 class LiteEthMACWishboneInterface(Module, AutoCSR):
-    def __init__(self, dw, nrxslots=2, ntxslots=2, endianness="big", timestamp=None, tx_write_only=False):
+    def __init__(self, dw, nrxslots=2, ntxslots=2, endianness="big", timestamp=None,
+        rxslots_read_only  = True,
+        txslots_write_only = False,
+    ):
         self.sink   = stream.Endpoint(eth_phy_description(dw))
         self.source = stream.Endpoint(eth_phy_description(dw))
         self.bus    = wishbone.Interface(data_width=dw)
@@ -34,7 +37,7 @@ class LiteEthMACWishboneInterface(Module, AutoCSR):
         for n in range(nrxslots):
             wb_rx_sram_ifs.append(wishbone.SRAM(
                 mem_or_size = self.sram.writer.mems[n],
-                read_only   = True,
+                read_only   = rxslots_read_only,
                 bus         = wishbone.Interface(data_width = dw)
             ))
 
@@ -43,7 +46,7 @@ class LiteEthMACWishboneInterface(Module, AutoCSR):
         for n in range(ntxslots):
             wb_tx_sram_ifs.append(wishbone.SRAM(
                 mem_or_size = self.sram.reader.mems[n],
-                write_only  = tx_write_only,
+                write_only  = txslots_write_only,
                 bus         = wishbone.Interface(data_width = dw)
             ))