diff --git a/example_designs/targets/etherbone.py b/example_designs/targets/etherbone.py
index ddc0c5d..24d39a3 100644
--- a/example_designs/targets/etherbone.py
+++ b/example_designs/targets/etherbone.py
@@ -10,7 +10,7 @@ class EtherboneSoC(BaseSoC):
         BaseSoC.__init__(self, platform,
             mac_address=0x10e2d5000000,
             ip_address="192.168.1.50")
-        self.submodules.etherbone = LiteEthEtherbone(self.core.udp, 20000, mode="master")
+        self.submodules.etherbone = LiteEthEtherbone(self.core.udp, 1234, mode="master")
         self.add_wb_master(self.etherbone.wishbone.bus)
 
 
diff --git a/test/test_etherbone.py b/test/test_etherbone.py
index 5078be3..8692089 100644
--- a/test/test_etherbone.py
+++ b/test/test_etherbone.py
@@ -24,7 +24,7 @@ class DUT(Module):
         self.submodules.etherbone_model = etherbone.Etherbone(self.udp_model, debug=False)
 
         self.submodules.core = LiteEthUDPIPCore(self.phy_model, mac_address, ip_address, 100000)
-        self.submodules.etherbone = LiteEthEtherbone(self.core.udp, 20000)
+        self.submodules.etherbone = LiteEthEtherbone(self.core.udp, 1234)
 
         self.submodules.sram = wishbone.SRAM(1024)
         self.submodules.interconnect = wishbone.InterconnectPointToPoint(self.etherbone.master.bus, self.sram.bus)