diff --git a/liteeth/phy/s7rgmii.py b/liteeth/phy/s7rgmii.py
index 6a562d1..22ec471 100644
--- a/liteeth/phy/s7rgmii.py
+++ b/liteeth/phy/s7rgmii.py
@@ -19,7 +19,7 @@ class LiteEthPHYRGMIITX(Module):
 
         # # #
 
-        tx_ctl_obuf = Signal()
+        tx_ctl_obuf  = Signal()
         tx_data_obuf = Signal(4)
 
         self.specials += [
@@ -51,12 +51,12 @@ class LiteEthPHYRGMIIRX(Module):
         delay_taps = int(delay/78e-12) # (78ps per tap)
         assert delay_taps < 32
 
-        rx_ctl_ibuf = Signal()
-        rx_ctl_idelay = Signal()
-        rx_ctl = Signal()
-        rx_data_ibuf = Signal(4)
+        rx_ctl_ibuf    = Signal()
+        rx_ctl_idelay  = Signal()
+        rx_ctl         = Signal()
+        rx_data_ibuf   = Signal(4)
         rx_data_idelay = Signal(4)
-        rx_data = Signal(8)
+        rx_data        = Signal(8)
 
         self.specials += [
             Instance("IBUF", i_I=pads.rx_ctl, o_O=rx_ctl_ibuf),
@@ -117,10 +117,10 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR):
         ]
 
         # TX
-        pll_locked = Signal()
-        pll_fb = Signal()
-        pll_clk_tx = Signal()
-        pll_clk_tx90 = Signal()
+        pll_locked      = Signal()
+        pll_fb          = Signal()
+        pll_clk_tx      = Signal()
+        pll_clk_tx90    = Signal()
         eth_tx_clk_obuf = Signal()
         self.specials += [
             Instance("PLLE2_BASE",
@@ -168,8 +168,8 @@ class LiteEthPHYRGMII(Module, AutoCSR):
     def __init__(self, clock_pads, pads, with_hw_init_reset=True):
         self.dw = 8
         self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads, pads, with_hw_init_reset)
-        self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(pads))
-        self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRGMIIRX(pads))
+        self.submodules.tx  = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(pads))
+        self.submodules.rx  = ClockDomainsRenamer("eth_rx")(LiteEthPHYRGMIIRX(pads))
         self.sink, self.source = self.tx.sink, self.rx.source
 
         if hasattr(pads, "mdc"):