From af5b9f433f12ffc7438f3145f22a5cbf21d64151 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 13 Jun 2023 18:09:15 +0200 Subject: [PATCH] README: Add PHY support/family table. --- README.md | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index f8db70c..c29b066 100644 --- a/README.md +++ b/README.md @@ -4,7 +4,7 @@ / /__/ / __/ -_) _// __/ _ \ /____/_/\__/\__/___/\__/_//_/ - Copyright 2012-2022 / EnjoyDigital + Copyright 2012-2023 / EnjoyDigital A small footprint and configurable Ethernet core powered by Migen & LiteX @@ -30,7 +30,16 @@ design flow by generating the verilog rtl that you will use as a standard core. ----------- PHY: - MII, RMII 100Mbps PHYs. - - GMII / RGMII /1000BaseX 1Gbps PHYs. + - GMII / RGMII / SGMII / 1000BaseX 1Gbps PHYs. + +| - | All | ECP5 | Spartan6 | Trion | Titanium | 7-Series | Ultrascale(+) | +|-------|-----|------|----------|-------|----------|----------|---------------| +| MII | X | X | X | X | X | X | X | +| RMII | X | X | X | X | X | X | X | +| GMII | | | X | | | X | X | +| RGMII | | X | X | X | X | X | X | +| SGMII | | | | | | X | X | + Core: - Configurable MAC (HW or SW interface) @@ -38,6 +47,7 @@ Core: Frontend: - Etherbone (Wishbone over UDP: Slave or Master support) + - UDP Streaming. [> FPGA Proven ---------------