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README: Add PHY support/family table.

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Florent Kermarrec 2023-06-13 18:09:15 +02:00
parent 9f69850697
commit af5b9f433f
1 changed files with 12 additions and 2 deletions
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README.md
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@ -4,7 +4,7 @@
/ /__/ / __/ -_) _// __/ _ \
/____/_/\__/\__/___/\__/_//_/
Copyright 2012-2022 / EnjoyDigital
Copyright 2012-2023 / EnjoyDigital
A small footprint and configurable Ethernet core
powered by Migen & LiteX
@ -30,7 +30,16 @@ design flow by generating the verilog rtl that you will use as a standard core.
-----------
PHY:
- MII, RMII 100Mbps PHYs.
- GMII / RGMII /1000BaseX 1Gbps PHYs.
- GMII / RGMII / SGMII / 1000BaseX 1Gbps PHYs.
| - | All | ECP5 | Spartan6 | Trion | Titanium | 7-Series | Ultrascale(+) |
|-------|-----|------|----------|-------|----------|----------|---------------|
| MII | X | X | X | X | X | X | X |
| RMII | X | X | X | X | X | X | X |
| GMII | | | X | | | X | X |
| RGMII | | X | X | X | X | X | X |
| SGMII | | | | | | X | X |
Core:
- Configurable MAC (HW or SW interface)
@ -38,6 +47,7 @@ Core:
Frontend:
- Etherbone (Wishbone over UDP: Slave or Master support)
- UDP Streaming.
[> FPGA Proven
---------------