diff --git a/liteeth/core/mac/core.py b/liteeth/core/mac/core.py
index 561fcf6..51c0ffc 100644
--- a/liteeth/core/mac/core.py
+++ b/liteeth/core/mac/core.py
@@ -67,12 +67,12 @@ class LiteEthMACCore(Module, AutoCSR):
         # Converters
         if dw != phy.dw:
             reverse = endianness == "big"
-            tx_converter = stream.Converter(eth_phy_description(dw),
-                                            eth_phy_description(phy.dw),
-                                            reverse=reverse)
-            rx_converter = stream.Converter(eth_phy_description(phy.dw),
-                                            eth_phy_description(dw),
-                                            reverse=reverse)
+            tx_converter = stream.StrideConverter(eth_phy_description(dw),
+                                                  eth_phy_description(phy.dw),
+                                                 reverse=reverse)
+            rx_converter = stream.StrideConverter(eth_phy_description(phy.dw),
+                                                  eth_phy_description(dw),
+                                                  reverse=reverse)
             self.submodules += ClockDomainsRenamer("eth_tx")(tx_converter)
             self.submodules += ClockDomainsRenamer("eth_rx")(rx_converter)
 
diff --git a/liteeth/core/udp.py b/liteeth/core/udp.py
index 8fa99f2..81b5e57 100644
--- a/liteeth/core/udp.py
+++ b/liteeth/core/udp.py
@@ -35,15 +35,15 @@ class LiteEthUDPCrossbar(LiteEthCrossbar):
         user_port = LiteEthUDPUserPort(dw)
         internal_port = LiteEthUDPUserPort(8)
         if dw != 8:
-            converter = stream.Converter(eth_udp_user_description(user_port.dw),
-                                  eth_udp_user_description(8))
+            converter = stream.StrideConverter(eth_udp_user_description(user_port.dw),
+                                               eth_udp_user_description(8))
             self.submodules += converter
             self.comb += [
                 user_port.sink.connect(converter.sink),
                 converter.source.connect(internal_port.sink)
             ]
-            converter = stream.Converter(eth_udp_user_description(8),
-                                  eth_udp_user_description(user_port.dw))
+            converter = stream.StrideConverter(eth_udp_user_description(8),
+                                               eth_udp_user_description(user_port.dw))
             self.submodules += converter
             self.comb += [
                 internal_port.source.connect(converter.sink),
diff --git a/liteeth/phy/mii.py b/liteeth/phy/mii.py
index d0e2cee..856939f 100644
--- a/liteeth/phy/mii.py
+++ b/liteeth/phy/mii.py
@@ -18,8 +18,8 @@ class LiteEthPHYMIITX(Module):
 
         if hasattr(pads, "tx_er"):
             self.sync += pads.tx_er.eq(0)
-        converter = stream.Converter(converter_description(8),
-                                     converter_description(4))
+        converter = stream.StrideConverter(converter_description(8),
+                                           converter_description(4))
         self.submodules += converter
         self.comb += [
             converter.sink.stb.eq(sink.stb),
@@ -39,8 +39,8 @@ class LiteEthPHYMIIRX(Module):
 
         # # #
 
-        converter = stream.Converter(converter_description(4),
-                                     converter_description(8))
+        converter = stream.StrideConverter(converter_description(4),
+                                           converter_description(8))
         converter = ResetInserter()(converter)
         self.submodules += converter
 
diff --git a/liteeth/phy/rmii.py b/liteeth/phy/rmii.py
index 4eb5141..65b5fd2 100644
--- a/liteeth/phy/rmii.py
+++ b/liteeth/phy/rmii.py
@@ -19,8 +19,8 @@ class LiteEthPHYRMIITX(Module):
 
         # # #
 
-        converter = stream.Converter(converter_description(8),
-                                     converter_description(2))
+        converter = stream.StrideConverter(converter_description(8),
+                                           converter_description(2))
         self.submodules += converter
         self.comb += [
             converter.sink.stb.eq(sink.stb),
@@ -40,8 +40,8 @@ class LiteEthPHYRMIIRX(Module):
 
         # # #
 
-        converter = stream.Converter(converter_description(2),
-                                     converter_description(8))
+        converter = stream.StrideConverter(converter_description(2),
+                                           converter_description(8))
         converter = ResetInserter()(converter)
         self.submodules += converter