From b0e72431234cbbf42a0f74f1a5f2bff145dfc043 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 16 May 2022 13:38:05 +0200 Subject: [PATCH] liteeth_gen: Add data_width support (For 32/8-bit datapath). --- examples/udp_s7phyrgmii.yml | 1 + liteeth/frontend/stream.py | 1 + liteeth/gen.py | 5 ++++- 3 files changed, 6 insertions(+), 1 deletion(-) diff --git a/examples/udp_s7phyrgmii.yml b/examples/udp_s7phyrgmii.yml index 3249448..3568eba 100644 --- a/examples/udp_s7phyrgmii.yml +++ b/examples/udp_s7phyrgmii.yml @@ -14,6 +14,7 @@ clk_freq: 125e6 core: udp mac_address: 0x10e2d5000000 ip_address: 192.168.1.50 +data_width: 8 # UDP Ports -------------------------------------------------------------------- udp_ports: { diff --git a/liteeth/frontend/stream.py b/liteeth/frontend/stream.py index fb188eb..2605416 100644 --- a/liteeth/frontend/stream.py +++ b/liteeth/frontend/stream.py @@ -50,6 +50,7 @@ class LiteEthStream2UDPTX(Module): source.ip_address.eq(ip_address), source.length.eq(level * (data_width//8)), source.data.eq(fifo.source.data), + source.last_be.eq({32:0b1000, 8:0b1}[data_width]), If(source.ready, fifo.source.ready.eq(1), NextValue(counter, counter + 1), diff --git a/liteeth/gen.py b/liteeth/gen.py index d1c7c62..e4c41e8 100755 --- a/liteeth/gen.py +++ b/liteeth/gen.py @@ -272,10 +272,13 @@ class UDPCore(PHYCore): PHYCore.__init__(self, platform, core_config) # Core ------------------------------------------------------------------------------------- + data_width = core_config.get("data_width", 8) self.submodules.core = LiteEthUDPIPCore(self.ethphy, mac_address = mac_address, ip_address = ip_address, - clk_freq = core_config["clk_freq"] + clk_freq = core_config["clk_freq"], + dw = data_width, + with_sys_datapath = (data_width == 32), ) # UDP Ports --------------------------------------------------------------------------------