liteeth_gen: Add data_width support (For 32/8-bit datapath).

This commit is contained in:
Florent Kermarrec 2022-05-16 13:38:05 +02:00
parent e2c1b81cd3
commit b0e7243123
3 changed files with 6 additions and 1 deletions

View File

@ -14,6 +14,7 @@ clk_freq: 125e6
core: udp core: udp
mac_address: 0x10e2d5000000 mac_address: 0x10e2d5000000
ip_address: 192.168.1.50 ip_address: 192.168.1.50
data_width: 8
# UDP Ports -------------------------------------------------------------------- # UDP Ports --------------------------------------------------------------------
udp_ports: { udp_ports: {

View File

@ -50,6 +50,7 @@ class LiteEthStream2UDPTX(Module):
source.ip_address.eq(ip_address), source.ip_address.eq(ip_address),
source.length.eq(level * (data_width//8)), source.length.eq(level * (data_width//8)),
source.data.eq(fifo.source.data), source.data.eq(fifo.source.data),
source.last_be.eq({32:0b1000, 8:0b1}[data_width]),
If(source.ready, If(source.ready,
fifo.source.ready.eq(1), fifo.source.ready.eq(1),
NextValue(counter, counter + 1), NextValue(counter, counter + 1),

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@ -272,10 +272,13 @@ class UDPCore(PHYCore):
PHYCore.__init__(self, platform, core_config) PHYCore.__init__(self, platform, core_config)
# Core ------------------------------------------------------------------------------------- # Core -------------------------------------------------------------------------------------
data_width = core_config.get("data_width", 8)
self.submodules.core = LiteEthUDPIPCore(self.ethphy, self.submodules.core = LiteEthUDPIPCore(self.ethphy,
mac_address = mac_address, mac_address = mac_address,
ip_address = ip_address, ip_address = ip_address,
clk_freq = core_config["clk_freq"] clk_freq = core_config["clk_freq"],
dw = data_width,
with_sys_datapath = (data_width == 32),
) )
# UDP Ports -------------------------------------------------------------------------------- # UDP Ports --------------------------------------------------------------------------------