liteeth_gen: Add data_width support (For 32/8-bit datapath).

examples/udp_s7phyrgmii.yml

@@ -14,6 +14,7 @@ clk_freq:    125e6
 core:        udp
 mac_address: 0x10e2d5000000
 ip_address:  192.168.1.50
+data_width:  8
 
 # UDP Ports --------------------------------------------------------------------
 udp_ports:   {

liteeth/frontend/stream.py

@@ -50,6 +50,7 @@ class LiteEthStream2UDPTX(Module):
                 source.ip_address.eq(ip_address),
                 source.length.eq(level * (data_width//8)),
                 source.data.eq(fifo.source.data),
+                source.last_be.eq({32:0b1000, 8:0b1}[data_width]),
                 If(source.ready,
                     fifo.source.ready.eq(1),
                     NextValue(counter, counter + 1),

liteeth/gen.py

@@ -272,10 +272,13 @@ class UDPCore(PHYCore):
         PHYCore.__init__(self, platform, core_config)
 
         # Core -------------------------------------------------------------------------------------
+        data_width = core_config.get("data_width", 8)
         self.submodules.core = LiteEthUDPIPCore(self.ethphy,
             mac_address = mac_address,
             ip_address  = ip_address,
-            clk_freq    = core_config["clk_freq"]
+            clk_freq    = core_config["clk_freq"],
+            dw          = data_width,
+            with_sys_datapath = (data_width == 32),
         )
 
         # UDP Ports --------------------------------------------------------------------------------