frontend/etherbone: Add LiteEthLastHandler to LiteEthEtherbonePacketRX for 64-bit data-width support.

This commit is contained in:
Florent Kermarrec 2024-09-12 13:33:39 +02:00
parent 0b5389feab
commit b1f916a447
1 changed files with 9 additions and 2 deletions

View File

@ -1,7 +1,7 @@
# #
# This file is part of LiteEth. # This file is part of LiteEth.
# #
# Copyright (c) 2015-2023 Florent Kermarrec <florent@enjoy-digital.fr> # Copyright (c) 2015-2024 Florent Kermarrec <florent@enjoy-digital.fr>
# SPDX-License-Identifier: BSD-2-Clause # SPDX-License-Identifier: BSD-2-Clause
""" """
@ -22,6 +22,8 @@ from liteeth.common import *
from litex.soc.interconnect import wishbone from litex.soc.interconnect import wishbone
from litex.soc.interconnect.packet import * from litex.soc.interconnect.packet import *
from liteeth.mac.common import LiteEthLastHandler
from liteeth.packet import Depacketizer, Packetizer from liteeth.packet import Depacketizer, Packetizer
# Etherbone Packet --------------------------------------------------------------------------------- # Etherbone Packet ---------------------------------------------------------------------------------
@ -84,8 +86,13 @@ class LiteEthEtherbonePacketRX(LiteXModule):
# # # # # #
self.last_handler = LiteEthLastHandler(eth_udp_user_description(32))
self.depacketizer = depacketizer = LiteEthEtherbonePacketDepacketizer() self.depacketizer = depacketizer = LiteEthEtherbonePacketDepacketizer()
self.comb += sink.connect(depacketizer.sink) self.comb += [
sink.connect(self.last_handler.sink),
self.last_handler.source.connect(depacketizer.sink),
]
self.fsm = fsm = FSM(reset_state="IDLE") self.fsm = fsm = FSM(reset_state="IDLE")
fsm.act("IDLE", fsm.act("IDLE",