From b1fd3e8092358019dbad867122a6036ef177dfa5 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 24 Nov 2020 10:19:52 +0100 Subject: [PATCH] bench/targets: increase buffer_depth to 256. --- bench/arty.py | 2 +- bench/colorlight_5a_75b.py | 2 +- bench/genesys2.py | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/bench/arty.py b/bench/arty.py index 97f5021..94389ed 100755 --- a/bench/arty.py +++ b/bench/arty.py @@ -42,7 +42,7 @@ class BenchSoC(SoCCore): pads = self.platform.request("eth"), with_hw_init_reset = False) self.add_csr("ethphy") - self.add_etherbone(phy=self.ethphy) + self.add_etherbone(phy=self.ethphy, buffer_depth=256) # SRAM ------------------------------------------------------------------------------------- self.add_ram("sram", 0x20000000, 0x1000) diff --git a/bench/colorlight_5a_75b.py b/bench/colorlight_5a_75b.py index 5c32431..a7e0d86 100755 --- a/bench/colorlight_5a_75b.py +++ b/bench/colorlight_5a_75b.py @@ -43,7 +43,7 @@ class BenchSoC(SoCCore): tx_delay = 0e-9, with_hw_init_reset = False) self.add_csr("ethphy") - self.add_etherbone(phy=self.ethphy) + self.add_etherbone(phy=self.ethphy, buffer_depth=256) # SRAM ------------------------------------------------------------------------------------- self.add_ram("sram", 0x20000000, 0x1000) diff --git a/bench/genesys2.py b/bench/genesys2.py index 3e9a7ca..f5490ba 100755 --- a/bench/genesys2.py +++ b/bench/genesys2.py @@ -42,7 +42,7 @@ class BenchSoC(SoCCore): pads = self.platform.request("eth"), with_hw_init_reset = False) self.add_csr("ethphy") - self.add_etherbone(phy=self.ethphy) + self.add_etherbone(phy=self.ethphy, buffer_depth=256) # SRAM ------------------------------------------------------------------------------------- self.add_ram("sram", 0x20000000, 0x1000)